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USPTO Patent Rankings Data through Dec 31, 2025
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Ryan Rakvic — 13 Patents

Intel: 13 patents #3,167 of 30,777Top 15%
San Jose, CA: #5,025 of 32,062 inventorsTop 20%
California: #47,433 of 386,348 inventorsTop 15%
Overall (All Time): #362,438 of 4,157,543Top 9%
13 Patents All Time
Ryan Rakvic has been granted 13 US patents while listed as an inventor at Intel. The first was granted in 2003 and the most recent in November 2014. Ryan Rakvic ranks #362,438 of 4,157,543 US inventors in our database (top 8.7%). Patent records list Ryan Rakvic in San Jose, CA, US.

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8887174 Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers Richard Hankins, Gautham Chinya, Hong Wang, Shivnandan Kaushik, Bryant Bigbee +7 more 2014-11-11 $20,178,000
8839258 Load balancing for multi-threaded applications via asymmetric power throttling Richard Hankins, Ed Grochowski, Hong Wang, Murali Annavaram, David K. Poulsen +3 more 2014-09-16 $19,366,000
8205200 Compiler-based scheduling optimization hints for user-level threads Shih-wei Liao, Richard Hankins, Hong Wang, Gansha Wu, Guei-Yuan Lueh +6 more 2012-06-19 $20,138,000
8108863 Load balancing for multi-threaded applications via asymmetric power throttling Richard Hankins, Ed Grochowski, Hong Wang, Murali Annavaram, David K. Poulsen +3 more 2012-01-31 $29,732,000
8010969 Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers Richard Hankins, Gautham Chinya, Hong Wang, Shivnandan Kaushik, Bryant Bigbee +7 more 2011-08-30 $23,929,000
7743233 Sequencer address management Hong Wang, Gautham Chinya, Richard Hankins, Shivnandan Kaushik, Bryant Bigbee +13 more 2010-06-22 $25,275,000
7665000 Meeting point thread characterization Antonio Gonzalez, Qiong Cai, Jose Gonzalez, Pedro Chaparro, Grigorios Magklis 2010-02-16 $21,778,000
7424576 Parallel cachelets John Shen, Deepak Limaye 2008-09-09 $18,766,000
7228402 Predicate register file write by an instruction with a pending instruction having data dependency Bohuslav Rychlik, Edward A. Brekelbaum, Bryan Black 2007-06-05 $17,840,000
7216201 Parallel cachelets John Shen, Deepak Limaye 2007-05-08 $17,693,000
7120749 Cache mechanism Youfeng Wu, Bryan Black, John Shen 2006-10-10 $14,351,000
6954848 Marking in history table instructions slowable/delayable for subsequent executions when result is not used immediately Christopher B. Wilkerson, Bryan Black, Edward T. Grochowski, John Shen, Edward A. Brekelbaum 2005-10-11 $27,235,000
6668306 Non-vital loads John Shen, Bohuslav Rychlik, Christopher B. Wilkerson, Jared W. Stark, IV, Hong Wang 2003-12-23 $55,491,000