Issued Patents All Time
Showing 25 most recent of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12399734 | Engine to enable high speed context switching via on-die storage | Altug Koker, Prasoonkumar Surti, David Puffer, Subramaniam Maiyuran, Abhishek R. Appu +7 more | 2025-08-26 |
| 12386617 | Gathering payload from arbitrary registers for send messages in a graphics environment | Supratim Pal, Chandra Gurram, Fan-Yin Tzeng, Subramaniam Maiyuran, Timothy Bauer +2 more | 2025-08-12 |
| 12346694 | Register file for systolic array | Chandra Gurram, Wei-Yu Chen, Fangwen Fu, Sabareesh Ganapathy, Varghese George +4 more | 2025-07-01 |
| 12333306 | High performance constant cache and constant access mechanisms | Subramaniam Maiyuran, Sudarshanram Shetty, Travis T. Schluessler, PingHang Cheung, Srividya Karumuri +3 more | 2025-06-17 |
| 12210905 | Multiple register allocation sizes for threads | Chandra Gurram, Wei-Yu Chen, Vikranth Vemulapalli, Subramaniam Maiyuran, Jorge Eduardo Parra Osorio +2 more | 2025-01-28 |
| 12190118 | Data locality enhancement for graphics processing units | Christopher J. Hughes, Prasoonkumar Surti, Adam T. Lake, Jill MacDonald Boyce, Subramaniam Maiyuran +6 more | 2025-01-07 |
| 12174783 | Systolic array of arbitrary physical and logical depth | Jorge Parra, Wei-Yu Chen, Kaiyu Chen, Varghese George, Junjie Gu +4 more | 2024-12-24 |
| 12164430 | Instruction prefetch mechanism | Vasileios Porpodas, Subramaniam Maiyuran, Wei-Yu Chen | 2024-12-10 |
| 12131402 | Page faulting and selective preemption | Altug Koker, Ingo Wald, David Puffer, Subramaniam Maiyuran, Prasoonkumar Surti +4 more | 2024-10-29 |
| 12067641 | Page faulting and selective preemption | Altug Koker, Ingo Wald, David Puffer, Subramaniam Maiyuran, Prasoonkumar Surti +4 more | 2024-08-20 |
| 12007935 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra +3 more | 2024-06-11 |
| 11954063 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra +3 more | 2024-04-09 |
| 11900502 | Compiler assisted register file write reduction | Chandra Gurram, Gang Chen, Subramaniam Maiyuran, Supratim Pal, Ashutosh Garg +3 more | 2024-02-13 |
| 11886875 | Systems and methods for performing nibble-sized operations on matrix elements | Elmoustapha Ould-Ahmed-Vall, Jonathan Pearce, Dan Baum, Michael Espig, Christopher J. Hughes +4 more | 2024-01-30 |
| 11861761 | Graphics processing unit processing and caching improvements | Subramaniam Maiyuran, Durgaprasad Bilagi, Joydeep Ray, Scott Janus, Sanjeev Jahagirdar +9 more | 2024-01-02 |
| 11803476 | Instruction prefetch mechanism | Vasileios Porpodas, Subramaniam Maiyuran, Wei-Yu Chen | 2023-10-31 |
| 11762696 | Hybrid low power homogenous grapics processing units | Abhishek R. Appu, Altug Koker, Balaji Vembu, Joydeep Ray, Kamal Sinha +16 more | 2023-09-19 |
| 11748302 | Engine to enable high speed context switching via on-die storage | Altug Koker, Prasoonkumar Surti, David Puffer, Subramaniam Maiyuran, Abhishek R. Appu +7 more | 2023-09-05 |
| 11726793 | Data locality enhancement for graphics processing units | Christopher J. Hughes, Prasoonkumar Surti, Adam T. Lake, Jill MacDonald Boyce, Subramaniam Maiyuran +6 more | 2023-08-15 |
| 11709793 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra +3 more | 2023-07-25 |
| 11669329 | Instructions and logic for vector multiply add with zero skipping | Supratim Pal, Sasikanth Avancha, Ishwar Bhati, Wei-Yu Chen, Dipankar Das +7 more | 2023-06-06 |
| 11640297 | Instruction and logic for systolic dot product with accumulate | Subramaniam Maiyuran, Supratim Pal, Ashutosh Garg, Chandra Gurram, Jorge Parra +10 more | 2023-05-02 |
| 11579878 | Register sharing mechanism to equally allocate disabled thread registers to active threads | Pratik J. Ashar, Supratim Pal, Subramaniam Maiyuran, Wei-Yu Chen | 2023-02-14 |
| 11537403 | Control flow mechanism for execution of graphics processor instructions using active channel packing | Subramaniam Maiyuran, Supratim Pal, Gang Chen, Ananda V. Kommaraju, Joy Chandra +10 more | 2022-12-27 |
| 11508338 | Register spill/fill using shared local memory space | Joydeep Ray, Altug Koker, Balaji Vembu, Murali Ramadoss, James Valerio +7 more | 2022-11-22 |