Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
VG

Varghese George — 148 Patents

Intel: 143 patents #104 of 30,777Top 1%
SSStmicroelectronics Sa: 3 patents #1,912 of 1,676Top 115%
NVIDIA: 2 patents #2,935 of 7,811Top 40%
Folsom, CA: #5 of 1,500 inventorsTop 1%
California: #1,029 of 386,348 inventorsTop 1%
Overall (All Time): #6,389 of 4,157,543Top 1%
148 Patents All Time
Varghese George has been granted 148 US patents while listed as an inventor at Intel. The first was granted in 2002 and the most recent in September 2025. Varghese George ranks #6,389 of 4,157,543 US inventors in our database (top 0.15%). Patent records list Varghese George in Folsom, CA, US.

Patents per Year

Patents granted per year, 2002 to 2025Bar chart with a peak of 28 patents in 2024.peak 282002: 2 patents20022003: 1 patents2004: 7 patents2005: 1 patents20052006: 4 patents2007: 5 patents2008: 1 patents20082009: 1 patents2010: 2 patents2011: 3 patents20112012: 1 patents2013: 4 patents2014: 7 patents20142015: 4 patents2016: 4 patents2017: 6 patents20172018: 5 patents2019: 1 patents2020: 4 patents20202021: 9 patents2022: 13 patents2023: 17 patents20232024: 28 patents2025: 18 patents2025

Issued Patents All Time

Showing 1–25 of 148 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12430128 Sharing register file usage between fused processing resources Subramaniam Maiyuran, Joydeep Ray, Ashutosh Garg, Jorge Parra, Shubh Shah +1 more 2025-09-30
12405787 Utilizing structured sparsity in systolic arrays Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Chandra Gurram, Chunhui Mei +10 more 2025-09-02
12399685 Systolic array having support for output sparsity Jorge Parra, Fangwen Fu, Subramaniam Maiyuran, Mike B. Macpherson, Supratim Pal +6 more 2025-08-26
12386779 Dynamic memory reconfiguration Joydeep Ray, Niranjan L. Cooray, Subramaniam Maiyuran, Altug Koker, Prasoonkumar Surti +11 more 2025-08-12
12373912 Prefetch status notification for memory prefetching Joydeep Ray, Aravindh Anantaraman, Valentin Andrei, Abhishek R. Appu, Nicolas C. Galoppo Von Borries +4 more 2025-07-29
12346694 Register file for systolic array Chandra Gurram, Wei-Yu Chen, Fangwen Fu, Sabareesh Ganapathy, Guei-Yuan Lueh +4 more 2025-07-01
12321310 Implicit fence for write messages Joydeep Ray, Altug Koker, Mike B. Macpherson, Aravindh Anantaraman, Abhishek R. Appu +3 more 2025-06-03
12306771 Efficient data sharing for graphics data processing operations Joydeep Ray, Altug Koker, Elmoustapha Ould-Ahmed-Vall, Michael Macpherson, Aravindh Anantaraman +4 more 2025-05-20
12293431 Sparse optimizations for a matrix accelerator architecture Joydeep Ray, Scott Janus, Subramaniam Maiyuran, Altug Koker, Abhishek R. Appu +12 more 2025-05-06
12254526 On chip dense memory for temporal buffering Altug Koker, Aravindh Anantaraman, Subramaniam Maiyuran, SungYe Kim, Valentin Andrei +6 more 2025-03-18
12242414 Data initialization techniques Abhishek R. Appu, Aravindh Anantaraman, Elmoustapha Ould-Ahmed-Vall, Valentin Andrei, Nicolas C. Galoppo Von Borries +5 more 2025-03-04
12242846 Supporting 8-bit floating point format operands in a computing architecture Naveen Mellempudi, Subramaniam Maiyuran, Fangwen Fu, Shuai Mu, Supratim Pal +1 more 2025-03-04
12229867 Graphics architecture including a neural network pipeline Hugues Labbe, DARREL PALKE, Sherine Abdelhak, Jill MacDonald Boyce, Scott Janus +10 more 2025-02-18
12229581 Virtualization and multi-tenancy support in graphics processors Rajesh M. Sankaran, Bret L. Toll, William C. Rash, Subramaniam Maiyuran, Gang Chen 2025-02-18
12223353 Systems and methods for synchronization of multi-thread lanes Valentin Andrei, Subramaniam Maiyuran, SungYe Kim, Altug Koker, Aravindh Anantaraman 2025-02-11
12210477 Systems and methods for improving cache efficiency and utilization Altug Koker, Joydeep Ray, Ben J. Ashbaugh, Jonathan Pearce, Abhishek R. Appu +19 more 2025-01-28
12204487 Graphics processor data access and sharing Altug Koker, Aravindh Anantaraman, Valentin Andrei, Abhishek R. Appu, Niranjan L. Cooray +11 more 2025-01-21
12198222 Architecture for block sparse operations on a systolic array Abhishek R. Appu, Subramaniam Maiyuran, Mike B. Macpherson, Fangwen Fu, Jiasheng Chen +3 more 2025-01-14
12182035 Systems and methods for cache optimization Altug Koker, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Abhishek R. Appu, Aravindh Anantaraman +11 more 2024-12-31 $16,542,000
12182062 Multi-tile memory management Abhishek R. Appu, Altug Koker, Aravindh Anantaraman, Elmoustapha Ould-Ahmed-Vall, Valentin Andrei +14 more 2024-12-31 $16,542,000
12174783 Systolic array of arbitrary physical and logical depth Jorge Parra, Wei-Yu Chen, Kaiyu Chen, Junjie Gu, Chandra Gurram +4 more 2024-12-24 $17,261,000
12153541 Cache structure and utilization Altug Koker, Lakshminarayanan Striramassarma, Aravindh Anantaraman, Valentin Andrei, Abhishek R. Appu +9 more 2024-11-26 $26,820,000
12141890 Enabling product SKUs based on chiplet configurations Altug Koker, Lance Cheney, Eric Finley, Sanjeev Jahagirdar, Josh B. Mastronarde +6 more 2024-11-12 $28,491,000
12141094 Systolic disaggregation within a matrix accelerator architecture Prasoonkumar Surti, Subramaniam Maiyuran, Valentin Andrei, Abhishek R. Appu, Altug Koker +6 more 2024-11-12 $28,491,000
12124383 Systems and methods for cache optimization Altug Koker, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Abhishek R. Appu, Aravindh Anantaraman +11 more 2024-10-22 $18,859,000