Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Kaiyu Chen — 11 Patents

Intel: 8 patents #4,914 of 30,777Top 20%
ASAlpha And Omega Semiconductor: 3 patents #88 of 159Top 60%
Santa Clara, CA: #1,605 of 9,301 inventorsTop 20%
California: #56,011 of 386,348 inventorsTop 15%
Overall (All Time): #435,149 of 4,157,543Top 15%
11 Patents All Time
Kaiyu Chen has been granted 11 US patents while listed as an inventor at Intel. The first was granted in 2009 and the most recent in December 2024. Kaiyu Chen ranks #435,149 of 4,157,543 US inventors in our database (top 10.5%). Patent records list Kaiyu Chen in Santa Clara, CA, US.

Issued Patents All Time

Showing 1–11 of 11 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12174783 Systolic array of arbitrary physical and logical depth Jorge Parra, Wei-Yu Chen, Varghese George, Junjie Gu, Chandra Gurram +4 more 2024-12-24 $17,261,000
10699362 Divergent control flow for fused EUs Pratik J. Ashar, Guei-Yuan Lueh, Subramaniam Maiyuran, Brent A. Schwartz, Darin Starkey 2020-06-30 $33,333,000
10692170 Software scoreboard information and synchronization Subramaniam Maiyuran, Supratim Pal, Jorge Parra, Chandra Gurram, Ashwin J. Shivani +9 more 2020-06-23 $27,746,000
10636112 Graphics processor register data re-use mechanism Slawomir Grajewski, Guei-Yuan Lueh, Subramaniam Maiyuran 2020-04-28 $36,717,000
10565670 Graphics processor register renaming mechanism Guei-Yuan Lueh, Subramaniam Maiyuran 2020-02-18 $23,634,000
10515431 Global optimal path determination utilizing parallel processing Yuenian Yang, Andrew J. Kuzma 2019-12-24 $26,956,000
10360654 Software scoreboard information and synchronization Subramaniam Maiyuran, Supratim Pal, Jorge Parra, Chandra Gurram, Ashwin J. Shivani +9 more 2019-07-23 $32,139,000
10282227 Efficient preemption for graphics processors Guei-Yuan Lueh, Subramaniam Maiyuran, Wei-Yu Chen 2019-05-07 $24,403,000
8084304 Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop Mengyu Pan, Zengyi He 2011-12-27 $1,461,000
7728385 Trench MOSFET with an ONO insulating layer sandwiched between an ESD protection module atop and a semiconductor substrate Mengyu Pan, Zengyi He 2010-06-01 $1,713,000
7585705 Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop Mengyu Pan, Zengyi He 2009-09-08