| 12174783 |
Systolic array of arbitrary physical and logical depth |
Jorge Parra, Wei-Yu Chen, Varghese George, Junjie Gu, Chandra Gurram +4 more |
2024-12-24 |
| 10699362 |
Divergent control flow for fused EUs |
Pratik J. Ashar, Guei-Yuan Lueh, Subramaniam Maiyuran, Brent A. Schwartz, Darin Starkey |
2020-06-30 |
| 10692170 |
Software scoreboard information and synchronization |
Subramaniam Maiyuran, Supratim Pal, Jorge Parra, Chandra Gurram, Ashwin J. Shivani +9 more |
2020-06-23 |
| 10636112 |
Graphics processor register data re-use mechanism |
Slawomir Grajewski, Guei-Yuan Lueh, Subramaniam Maiyuran |
2020-04-28 |
| 10565670 |
Graphics processor register renaming mechanism |
Guei-Yuan Lueh, Subramaniam Maiyuran |
2020-02-18 |
| 10515431 |
Global optimal path determination utilizing parallel processing |
Yuenian Yang, Andrew J. Kuzma |
2019-12-24 |
| 10360654 |
Software scoreboard information and synchronization |
Subramaniam Maiyuran, Supratim Pal, Jorge Parra, Chandra Gurram, Ashwin J. Shivani +9 more |
2019-07-23 |
| 10282227 |
Efficient preemption for graphics processors |
Guei-Yuan Lueh, Subramaniam Maiyuran, Wei-Yu Chen |
2019-05-07 |
| 8084304 |
Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop |
Mengyu Pan, Zengyi He |
2011-12-27 |
| 7728385 |
Trench MOSFET with an ONO insulating layer sandwiched between an ESD protection module atop and a semiconductor substrate |
Mengyu Pan, Zengyi He |
2010-06-01 |
| 7585705 |
Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop |
Mengyu Pan, Zengyi He |
2009-09-08 |