| 12430128 |
Sharing register file usage between fused processing resources |
Subramaniam Maiyuran, Varghese George, Joydeep Ray, Ashutosh Garg, Shubh Shah +1 more |
2025-09-30 |
|
| 12405787 |
Utilizing structured sparsity in systolic arrays |
Subramaniam Maiyuran, Ashutosh Garg, Chandra Gurram, Chunhui Mei, Durgesh Borkar +10 more |
2025-09-02 |
|
| 12399685 |
Systolic array having support for output sparsity |
Fangwen Fu, Subramaniam Maiyuran, Varghese George, Mike B. Macpherson, Supratim Pal +6 more |
2025-08-26 |
|
| 12346694 |
Register file for systolic array |
Chandra Gurram, Wei-Yu Chen, Fangwen Fu, Sabareesh Ganapathy, Varghese George +4 more |
2025-07-01 |
|
| 12189571 |
Dual pipeline parallel systolic array |
Jiasheng Chen, Supratim Pal, Fangwen Fu, Sabareesh Ganapathy, Chandra Gurram +2 more |
2025-01-07 |
|
| 12190158 |
Using sparsity metadata to reduce systolic array power consumption |
Supratim Pal, Jiasheng Chen, Chandra Gurram |
2025-01-07 |
|
| 12174783 |
Systolic array of arbitrary physical and logical depth |
Wei-Yu Chen, Kaiyu Chen, Varghese George, Junjie Gu, Chandra Gurram +4 more |
2024-12-24 |
$17,261,000 |
| 12093213 |
Computing efficient cross channel operations in parallel computing machines using systolic arrays |
Subramaniam Maiyuran, Supratim Pal, Chandra Gurram |
2024-09-17 |
$19,251,000 |
| 12039001 |
Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs |
Subramaniam Maiyuran, Supratim Pal, Ashutosh Garg, Shubra Marwaha, Chandra Gurram +3 more |
2024-07-16 |
$26,089,000 |
| 12008067 |
Sparse matrix multiplication acceleration mechanism |
Subramaniam Maiyuran, Mathew Nevin, Ashutosh Garg, Shubra Marwaha, Shubh Shah |
2024-06-11 |
$21,221,000 |
| 12007935 |
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format |
Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Supratim Pal, Chandra Gurram +3 more |
2024-06-11 |
$21,221,000 |
| 11977885 |
Utilizing structured sparsity in systolic arrays |
Subramaniam Maiyuran, Ashutosh Garg, Chandra Gurram, Chunhui Mei, Durgesh Borkar +10 more |
2024-05-07 |
$26,756,000 |
| 11954063 |
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format |
Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Supratim Pal, Chandra Gurram +3 more |
2024-04-09 |
$27,197,000 |
| 11900502 |
Compiler assisted register file write reduction |
Chandra Gurram, Gang Chen, Subramaniam Maiyuran, Supratim Pal, Ashutosh Garg +3 more |
2024-02-13 |
$18,546,000 |
| 11709793 |
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format |
Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Supratim Pal, Chandra Gurram +3 more |
2023-07-25 |
$28,608,000 |
| 11669329 |
Instructions and logic for vector multiply add with zero skipping |
Supratim Pal, Sasikanth Avancha, Ishwar Bhati, Wei-Yu Chen, Dipankar Das +7 more |
2023-06-06 |
$21,341,000 |
| 11669490 |
Computing efficient cross channel operations in parallel computing machines using systolic arrays |
Subramaniam Maiyuran, Supratim Pal, Chandra Gurram |
2023-06-06 |
$21,341,000 |
| 11640297 |
Instruction and logic for systolic dot product with accumulate |
Subramaniam Maiyuran, Guei-Yuan Lueh, Supratim Pal, Ashutosh Garg, Chandra Gurram +10 more |
2023-05-02 |
$21,235,000 |
| 11636174 |
Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs |
Subramaniam Maiyuran, Supratim Pal, Ashutosh Garg, Shubra Marwaha, Chandra Gurram +3 more |
2023-04-25 |
$19,274,000 |
| 11361496 |
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format |
Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Supratim Pal, Chandra Gurram +3 more |
2022-06-14 |
$16,878,000 |
| 11327754 |
Method and apparatus for approximation using polynomials |
Dan Baum, Robert S. Chappell, Michael Espig, Varghese George, Alexander Heinecke +5 more |
2022-05-10 |
$19,182,000 |
| 11321799 |
Compiler assisted register file write reduction |
Chandra Gurram, Gang Chen, Subramaniam Maiyuran, Supratim Pal, Ashutosh Garg +3 more |
2022-05-03 |
$16,346,000 |
| 11314515 |
Instructions and logic for vector multiply add with zero skipping |
Supratim Pal, Sasikanth Avancha, Ishwar Bhati, Wei-Yu Chen, Dipankar Das +7 more |
2022-04-26 |
$25,630,000 |
| 11294670 |
Method and apparatus for performing reduction operations on a plurality of associated data element values |
Christopher J. Hughes, Jonathan Pearce, Guei-Yuan Lueh, Elmoustapha Ould-Ahmed-Vall, Prasoonkumar Surti +2 more |
2022-04-05 |
$18,322,000 |
| 11221848 |
Sharing register file usage between fused processing resources |
Subramaniam Maiyuran, Varghese George, Joydeep Ray, Ashutosh Garg, Shubh Shah +1 more |
2022-01-11 |
$33,310,000 |
