Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Shubra Marwaha — 16 Patents

Intel: 16 patents #2,596 of 30,777Top 9%
Folsom, CA: #155 of 1,500 inventorsTop 15%
California: #37,952 of 386,348 inventorsTop 10%
Overall (All Time): #284,196 of 4,157,543Top 7%
16 Patents All Time
Shubra Marwaha has been granted 16 US patents while listed as an inventor at Intel. The first was granted in 2021 and the most recent in September 2025. Shubra Marwaha ranks #284,196 of 4,157,543 US inventors in our database (top 6.8%). Patent records list Shubra Marwaha in Folsom, CA, US.

Patents per Year

Patents granted per year, 2021 to 2025Bar chart with a peak of 5 patents in 2024.peak 52021: 3 patents20212022: 3 patents20222023: 3 patents20232024: 5 patents20242025: 2 patents2025

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12430128 Sharing register file usage between fused processing resources Subramaniam Maiyuran, Varghese George, Joydeep Ray, Ashutosh Garg, Jorge Parra +1 more 2025-09-30
12405787 Utilizing structured sparsity in systolic arrays Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Chandra Gurram, Chunhui Mei +10 more 2025-09-02
12039001 Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs Subramaniam Maiyuran, Jorge Parra, Supratim Pal, Ashutosh Garg, Chandra Gurram +3 more 2024-07-16 $26,089,000
12007935 Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format Subramaniam Maiyuran, Ashutosh Garg, Supratim Pal, Jorge Parra, Chandra Gurram +3 more 2024-06-11 $21,221,000
12008067 Sparse matrix multiplication acceleration mechanism Subramaniam Maiyuran, Mathew Nevin, Jorge Parra, Ashutosh Garg, Shubh Shah 2024-06-11 $21,221,000
11977885 Utilizing structured sparsity in systolic arrays Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Chandra Gurram, Chunhui Mei +10 more 2024-05-07 $26,756,000
11954063 Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format Subramaniam Maiyuran, Ashutosh Garg, Supratim Pal, Jorge Parra, Chandra Gurram +3 more 2024-04-09 $27,197,000
11709793 Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format Subramaniam Maiyuran, Ashutosh Garg, Supratim Pal, Jorge Parra, Chandra Gurram +3 more 2023-07-25 $28,608,000
11640297 Instruction and logic for systolic dot product with accumulate Subramaniam Maiyuran, Guei-Yuan Lueh, Supratim Pal, Ashutosh Garg, Chandra Gurram +10 more 2023-05-02 $21,235,000
11636174 Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs Subramaniam Maiyuran, Jorge Parra, Supratim Pal, Ashutosh Garg, Chandra Gurram +3 more 2023-04-25 $19,274,000
11416580 Dot product multiplier mechanism Nevin Mathew, Ashutosh Garg 2022-08-16 $17,788,000
11361496 Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format Subramaniam Maiyuran, Ashutosh Garg, Supratim Pal, Jorge Parra, Chandra Gurram +3 more 2022-06-14 $16,878,000
11221848 Sharing register file usage between fused processing resources Subramaniam Maiyuran, Varghese George, Joydeep Ray, Ashutosh Garg, Jorge Parra +1 more 2022-01-11 $33,310,000
11204977 Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs Subramaniam Maiyuran, Jorge Parra, Supratim Pal, Ashutosh Garg, Chandra Gurram +3 more 2021-12-21 $33,282,000
11188618 Sparse matrix multiplication acceleration mechanism Subramaniam Maiyuran, Mathew Nevin, Jorge Parra, Ashutosh Garg, Shubh Shah 2021-11-30 $30,212,000
11042370 Instruction and logic for systolic dot product with accumulate Subramaniam Maiyuran, Guei-Yuan Lueh, Supratim Pal, Ashutosh Garg, Chandra Gurram +10 more 2021-06-22 $40,504,000