Issued Patents All Time
Showing 25 most recent of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12405787 | Utilizing structured sparsity in systolic arrays | Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Chandra Gurram, Chunhui Mei +10 more | 2025-09-02 |
| 12399685 | Systolic array having support for output sparsity | Jorge Parra, Fangwen Fu, Subramaniam Maiyuran, Varghese George, Mike B. Macpherson +6 more | 2025-08-26 |
| 12386617 | Gathering payload from arbitrary registers for send messages in a graphics environment | Chandra Gurram, Fan-Yin Tzeng, Subramaniam Maiyuran, Guei-Yuan Lueh, Timothy Bauer +2 more | 2025-08-12 |
| 12375262 | Fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) workloads in a graphics environment | Wajdi K. Feghali, Changwon Rhee, Wei-Yu Chen, Timothy Bauer, Alexander Lyashevsky | 2025-07-29 |
| 12346694 | Register file for systolic array | Chandra Gurram, Wei-Yu Chen, Fangwen Fu, Sabareesh Ganapathy, Varghese George +4 more | 2025-07-01 |
| 12242846 | Supporting 8-bit floating point format operands in a computing architecture | Naveen Mellempudi, Subramaniam Maiyuran, Varghese George, Fangwen Fu, Shuai Mu +1 more | 2025-03-04 |
| 12236238 | Large integer multiplication enhancements for graphics environment | Li-An Tang, Changwon Rhee, Timothy Bauer, Alexander Lyashevsky, Jiasheng Chen | 2025-02-25 |
| 12210905 | Multiple register allocation sizes for threads | Chandra Gurram, Wei-Yu Chen, Vikranth Vemulapalli, Subramaniam Maiyuran, Jorge Eduardo Parra Osorio +2 more | 2025-01-28 |
| 12189571 | Dual pipeline parallel systolic array | Jorge Parra, Jiasheng Chen, Fangwen Fu, Sabareesh Ganapathy, Chandra Gurram +2 more | 2025-01-07 |
| 12190158 | Using sparsity metadata to reduce systolic array power consumption | Jorge Parra, Jiasheng Chen, Chandra Gurram | 2025-01-07 |
| 12174783 | Systolic array of arbitrary physical and logical depth | Jorge Parra, Wei-Yu Chen, Kaiyu Chen, Varghese George, Junjie Gu +4 more | 2024-12-24 |
| 12093213 | Computing efficient cross channel operations in parallel computing machines using systolic arrays | Subramaniam Maiyuran, Jorge Parra, Chandra Gurram | 2024-09-17 |
| 12039001 | Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs | Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Shubra Marwaha, Chandra Gurram +3 more | 2024-07-16 |
| 12007935 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Jorge Parra, Chandra Gurram +3 more | 2024-06-11 |
| 11977885 | Utilizing structured sparsity in systolic arrays | Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Chandra Gurram, Chunhui Mei +10 more | 2024-05-07 |
| 11954063 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Jorge Parra, Chandra Gurram +3 more | 2024-04-09 |
| 11900502 | Compiler assisted register file write reduction | Chandra Gurram, Gang Chen, Subramaniam Maiyuran, Ashutosh Garg, Jorge Parra +3 more | 2024-02-13 |
| 11709793 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Jorge Parra, Chandra Gurram +3 more | 2023-07-25 |
| 11669490 | Computing efficient cross channel operations in parallel computing machines using systolic arrays | Subramaniam Maiyuran, Jorge Parra, Chandra Gurram | 2023-06-06 |
| 11669329 | Instructions and logic for vector multiply add with zero skipping | Sasikanth Avancha, Ishwar Bhati, Wei-Yu Chen, Dipankar Das, Ashutosh Garg +7 more | 2023-06-06 |
| 11640297 | Instruction and logic for systolic dot product with accumulate | Subramaniam Maiyuran, Guei-Yuan Lueh, Ashutosh Garg, Chandra Gurram, Jorge Parra +10 more | 2023-05-02 |
| 11636174 | Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs | Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Shubra Marwaha, Chandra Gurram +3 more | 2023-04-25 |
| 11593069 | Use of a single instruction set architecture (ISA) instruction for vector normalization | Abhishek Rhisheekesan, Shashank Lakshminarayana, Subramaniam Maiyuran | 2023-02-28 |
| 11579878 | Register sharing mechanism to equally allocate disabled thread registers to active threads | Pratik J. Ashar, Subramaniam Maiyuran, Wei-Yu Chen, Guei-Yuan Lueh | 2023-02-14 |
| 11537403 | Control flow mechanism for execution of graphics processor instructions using active channel packing | Subramaniam Maiyuran, Guei-Yuan Lueh, Gang Chen, Ananda V. Kommaraju, Joy Chandra +10 more | 2022-12-27 |