Issued Patents All Time
Showing 26–48 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11507375 | Hierarchical general register file (GRF) for execution block | Abhishek R. Appu, Altug Koker, Joydeep Ray, Kamal Sinha, Kiran C. Veernapu +7 more | 2022-11-22 |
| 11443407 | Sparse matrix optimization mechanism | Namita Sharma, Biju P. Simon, Tovinakere D. Vivek | 2022-09-13 |
| 11361496 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Jorge Parra, Chandra Gurram +3 more | 2022-06-14 |
| 11321799 | Compiler assisted register file write reduction | Chandra Gurram, Gang Chen, Subramaniam Maiyuran, Ashutosh Garg, Jorge Parra +3 more | 2022-05-03 |
| 11314515 | Instructions and logic for vector multiply add with zero skipping | Sasikanth Avancha, Ishwar Bhati, Wei-Yu Chen, Dipankar Das, Ashutosh Garg +7 more | 2022-04-26 |
| 11204977 | Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs | Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Shubra Marwaha, Chandra Gurram +3 more | 2021-12-21 |
| 11182337 | Computing efficient cross channel operations in parallel computing machines using systolic arrays | Subramaniam Maiyuran, Jorge Parra, Chandra Gurram | 2021-11-23 |
| 11157238 | Use of a single instruction set architecture (ISA) instruction for vector normalization | Abhishek Rhisheekesan, Shashank Lakshminarayana, Subramaniam Maiyuran | 2021-10-26 |
| 11127108 | Sparse matrix optimization mechanism | Namita Sharma, Biju P. Simon, Tovinakere D. Vivek | 2021-09-21 |
| 11042370 | Instruction and logic for systolic dot product with accumulate | Subramaniam Maiyuran, Guei-Yuan Lueh, Ashutosh Garg, Chandra Gurram, Jorge Parra +10 more | 2021-06-22 |
| 11010163 | Hierarchical general register file (GRF) for execution block | Abhishek R. Appu, Altug Koker, Joydeep Ray, Kamal Sinha, Kiran C. Veernapu +7 more | 2021-05-18 |
| 10990409 | Control flow mechanism for execution of graphics processor instructions using active channel packing | Subramaniam Maiyuran, Guei-Yuan Lueh, Gang Chen, Ananda V. Kommaraju, Joy Chandra +10 more | 2021-04-27 |
| 10983794 | Register sharing mechanism | Guei-Yuan Lueh, Subramaniam Maiyuran, Weiyu Chen, Konrad Trifunovic, Chandra Gurram +3 more | 2021-04-20 |
| 10839478 | Accumulator pooling mechanism | Guei-Yuan Lueh, Subramaniam Maiyuran, Wei-Yu Chen, Konrad Trifunovic, Chandra Gurram +3 more | 2020-11-17 |
| 10789071 | Dynamic thread splitting having multiple instruction pointers for the same thread | Hema Chand Nalluri, Subramaniam Maiyuran, Joy Chandra | 2020-09-29 |
| 10698689 | Recompiling GPU code based on spill/fill instructions and number of stall cycles | Pratik J. Ashar, Subramaniam Maiyuran, Wei-Yu Chen, Guei-Yuan Lueh | 2020-06-30 |
| 10692170 | Software scoreboard information and synchronization | Subramaniam Maiyuran, Jorge Parra, Chandra Gurram, Ashwin J. Shivani, Ashutosh Garg +9 more | 2020-06-23 |
| 10423415 | Hierarchical general register file (GRF) for execution block | Abhishek R. Appu, Altug Koker, Joydeep Ray, Kamal Sinha, Kiran C. Veernapu +7 more | 2019-09-24 |
| 10360654 | Software scoreboard information and synchronization | Subramaniam Maiyuran, Jorge Parra, Chandra Gurram, Ashwin J. Shivani, Ashutosh Garg +9 more | 2019-07-23 |
| 10152452 | Source operand read suppression for graphics processors | Subramaniam Maiyuran, Mark Charles Davis | 2018-12-11 |
| 9880839 | Instruction that performs a scatter write | Wei-Yu Chen, Guei-Yuan Lueh, Subramaniam Maiyuran | 2018-01-30 |
| 9632801 | Banked memory access efficiency by a graphics processor | Murali Sundaresan | 2017-04-25 |
| 9245495 | Simplification of local contrast compensation by using weighted look-up table | Niraj Gupta, Mahesh B. Chappalli, Yi-Jen Chiu, Hong Jiang | 2016-01-26 |