Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12197358 | Scalable I/O virtualization interrupt and scheduling | David Puffer, Ankur N. Shah, Niranjan L. Cooray, Bryan R. White, Balaji Vembu +1 more | 2025-01-14 |
| 11748283 | Scalable I/O virtualization interrupt and scheduling | David Puffer, Ankur N. Shah, Niranjan L. Cooray, Bryan R. White, Balaji Vembu +1 more | 2023-09-05 |
| 11726826 | Dynamic load balancing of compute assets among different compute contexts | James Valerio, Vasanth Ranganathan, Joydeep Ray, Rahul A. KULKARNI, Abhishek R. Appu +1 more | 2023-08-15 |
| 11481864 | Workload scheduling and distribution on a distributed graphics device | Balaji Vembu, Brandon Fliflet, James Valerio, Michael Apodaca, Ben J. Ashbaugh +8 more | 2022-10-25 |
| 11321262 | Interconnected systems fence mechanism | Ankur N. Shah, Joydeep Ray, Aditya Navale, Altug Koker, Murali Ramadoss +6 more | 2022-05-03 |
| 11288191 | Range based flushing mechanism | Aditya Navale, Altug Koker, Brandon Fliflet, Jeffery S. Boles, James Valerio +3 more | 2022-03-29 |
| 11281837 | Router-based transaction routing for toggle reduction | Balaji Vembu, Santosh Kumar Tripathy, Altug Koker, Pattabhiraman K | 2022-03-22 |
| 11232531 | Method and apparatus for efficient loop processing in a graphics hardware front end | Balaji Vembu, Peter L. Doyle, Michael Apodaca | 2022-01-25 |
| 11145115 | Position only shader context submission through a render command streamer | Murali Ramadoss, Balaji Vembu, Michael Apodaca, Jeffery S. Boles | 2021-10-12 |
| 11074109 | Dynamic load balancing of compute assets among different compute contexts | James Valerio, Vasanth Ranganathan, Joydeep Ray, Rahul A. KULKARNI, Abhishek R. Appu +1 more | 2021-07-27 |
| 10997686 | Workload scheduling and distribution on a distributed graphics device | Balaji Vembu, Brandon Fliflet, James Valerio, Michael Apodaca, Ben J. Ashbaugh +8 more | 2021-05-04 |
| 10908939 | Efficient fine grained processing of graphics workloads in a virtualized environment | Balaji Vembu, Altug Koker, David Puffer, Murali Ramadoss, Bryan R. White +1 more | 2021-02-02 |
| 10885880 | Programmable controller and command cache for graphics processors | Jeffery S. Boles, Balaji Vembu, Michael Apodaca, Altug Koker, Lalit K. Saptarshi | 2021-01-05 |
| 10796472 | Method and apparatus for simultaneously executing multiple contexts on a graphics engine | Michael Apodaca, Ankur N. Shah, Ben J. Ashbaugh, Brandon Fliflet, Pattabhiraman K +8 more | 2020-10-06 |
| 10789071 | Dynamic thread splitting having multiple instruction pointers for the same thread | Supratim Pal, Subramaniam Maiyuran, Joy Chandra | 2020-09-29 |
| 10672176 | Apparatus and method for processing commands in tile-based renderers | Balaji Vembu, Peter L. Doyle, Michael Apodaca, Jeffery S. Boles | 2020-06-02 |
| 10613972 | Dynamic configuration of caches in a multi-context supported graphics processor | Balaji Vembu, Pattabhiraman K, Altug Koker | 2020-04-07 |
| 10579382 | Method and apparatus for a scalable interrupt infrastructure | Rajesh M. Sankaran, Ankur N. Shah, Bryan R. White, David Puffer, Murali Ramadoss +3 more | 2020-03-03 |
| 10522114 | Programmable controller and command cache for graphics processors | Jeffery S. Boles, Balaji Vembu, Michael Apodaca, Altug Koker, Lalit K. Saptarshi | 2019-12-31 |
| 10410311 | Method and apparatus for efficient submission of workload to a high performance graphics sub-system | Balaji Vembu, Kritika Bala, Murali Ramadoss, Jeffery S. Boles, Jeffrey S. Frizzell +1 more | 2019-09-10 |
| 10303902 | Hardware assist for privilege access violation checks | Aditya Navale, Murali Ramadoss | 2019-05-28 |
| 10210655 | Position only shader context submission through a render command streamer | Murali Ramadoss, Balaji Vembu, Michael Apodaca, Jeffery S. Boles | 2019-02-19 |
| 10192281 | Graphics command parsing mechanism | Jeffery S. Boles, Balaji Vembu, Pritav Shah, Michael Apodaca, Murali Ramadoss +1 more | 2019-01-29 |
| 10078879 | Process synchronization between engines using data in a memory location | Aditya Navale | 2018-09-18 |
| 10068307 | Command processing for graphics tile-based rendering | Balaji Vembu, Peter L. Doyle, Michael Apodaca, Jeffery S. Boles | 2018-09-04 |