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USPTO Patent Rankings Data through Dec 31, 2025
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James Valerio — 52 Patents

Intel: 52 patents #607 of 30,777Top 2%
North Plains, OR: #5 of 81 inventorsTop 7%
Oregon: #655 of 28,073 inventorsTop 3%
Overall (All Time): #50,240 of 4,157,543Top 2%
52 Patents All Time
James Valerio has been granted 52 US patents while listed as an inventor at Intel. The first was granted in 1989 and the most recent in December 2025. James Valerio ranks #50,240 of 4,157,543 US inventors in our database (top 1.2%). Patent records list James Valerio in North Plains, OR, US.

Issued Patents All Time

Showing 1–25 of 52 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12487824 Immediate offset of load store and atomic instructions Joydeep Ray, Abhishek R. Appu, Timothy Bauer, Wei Chen, Subramaniam Maiyuran +5 more 2025-12-02
12333310 Base plus offset addressing for load/store messages John Wiegert, Joydeep Ray, Timothy Bauer 2025-06-17
12182062 Multi-tile memory management Abhishek R. Appu, Altug Koker, Aravindh Anantaraman, Elmoustapha Ould-Ahmed-Vall, Valentin Andrei +14 more 2024-12-31 $16,542,000
12164952 Barrier state save and restore for preemption in a graphics environment Vasanth Ranganathan, Joydeep Ray, Abhishek R. Appu, Alan M. Curtis, Prathamesh Raghunath Shinde +3 more 2024-12-10 $13,394,000
12124852 Instruction prefetch based on thread dispatch commands Vasanth Ranganathan, Joydeep Ray, Pradeep Ramani 2024-10-22 $18,859,000
12099461 Multi-tile memory management Abhishek R. Appu, Altug Koker, Aravindh Anantaraman, Elmoustapha Ould-Ahmed-Vall, Valentin Andrei +14 more 2024-09-24 $33,787,000
12014183 Base plus offset addressing for load/store messages John Wiegert, Joydeep Ray, Timothy Bauer 2024-06-18 $26,452,000
11995737 Thread scheduling over compute blocks for power optimization Altug Koker, Balaji Vembu, Joydeep Ray, Abhishek R. Appu 2024-05-28 $30,739,000
11977895 Hierarchical thread scheduling based on multiple barriers Sabareesh Ganapathy, Fangwen Fu, Hong Jiang 2024-05-07 $26,756,000
11762662 Instruction prefetch based on thread dispatch commands Vasanth Ranganathan, Joydeep Ray, Pradeep Ramani 2023-09-19 $20,015,000
11726826 Dynamic load balancing of compute assets among different compute contexts Vasanth Ranganathan, Joydeep Ray, Rahul A. KULKARNI, Abhishek R. Appu, Jeffery S. Boles +1 more 2023-08-15 $18,845,000
11508338 Register spill/fill using shared local memory space Joydeep Ray, Altug Koker, Balaji Vembu, Murali Ramadoss, Guei-Yuan Lueh +7 more 2022-11-22 $12,862,000
11494232 Memory-based software barriers Altug Koker, Joydeep Ray, Balaji Vembu, Abhishek R. Appu 2022-11-08 $15,080,000
11481864 Workload scheduling and distribution on a distributed graphics device Balaji Vembu, Brandon Fliflet, Michael Apodaca, Ben J. Ashbaugh, Hema Chand Nalluri +8 more 2022-10-25 $11,792,000
11436695 Coarse grain coherency Joydeep Ray, Altug Koker, David Puffer, Abhishek R. Appu, Stephen Junkins 2022-09-06 $12,766,000
11409579 Multiple independent synchonization named barrier within a thread group Vasanth Ranganathan, Joydeep Ray 2022-08-09 $13,688,000
11354768 Intelligent graphics dispatching mechanism Balaji Vembu, Murali Ramadoss, Guei-Yuan Lueh, Subramaniam Maiyuran, Abhishek R. Appu +4 more 2022-06-07 $12,864,000
11321262 Interconnected systems fence mechanism Hema Chand Nalluri, Ankur N. Shah, Joydeep Ray, Aditya Navale, Altug Koker +6 more 2022-05-03 $16,346,000
11301384 Partial write management in a multi-tiled compute engine Joydeep Ray, Ben J. Ashbaugh, Lakshminarayanan Striramassarma 2022-04-12 $16,909,000
11288191 Range based flushing mechanism Hema Chand Nalluri, Aditya Navale, Altug Koker, Brandon Fliflet, Jeffery S. Boles +3 more 2022-03-29 $28,068,000
11263152 Replacement policies for a hybrid hierarchical cache Abhishek R. Appu, Joydeep Ray, Altug Koker, Prasoonkumar Surti, Balaji Vembu +3 more 2022-03-01 $16,941,000
11227360 Thread scheduling over compute blocks for power optimization Altug Koker, Balaji Vembu, Joydeep Ray, Abhishek R. Appu 2022-01-18 $31,898,000
11194722 Apparatus and method for improved cache utilization and efficiency on a many core processor Bharath Narasimha Swamy, Joydeep Ray, Rama Kishan V. Malladi, Abhishek R. Appu 2021-12-07 $28,128,000
11175949 Microcontroller-based flexible thread scheduling launching in computing environments Kiran C. Veernapu, Kamlesh Pillai, Joydeep Ray, Abhishek R. Appu 2021-11-16 $23,453,000
11176083 Switching crossbar for graphics pipeline Joydeep Ray, Altug Koker, Abhishek R. Appu, Vasanth Ranganathan 2021-11-16 $23,453,000