| 12405787 |
Utilizing structured sparsity in systolic arrays |
Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Chunhui Mei, Durgesh Borkar +10 more |
2025-09-02 |
|
| 12399685 |
Systolic array having support for output sparsity |
Jorge Parra, Fangwen Fu, Subramaniam Maiyuran, Varghese George, Mike B. Macpherson +6 more |
2025-08-26 |
|
| 12386617 |
Gathering payload from arbitrary registers for send messages in a graphics environment |
Supratim Pal, Fan-Yin Tzeng, Subramaniam Maiyuran, Guei-Yuan Lueh, Timothy Bauer +2 more |
2025-08-12 |
|
| 12346694 |
Register file for systolic array |
Wei-Yu Chen, Fangwen Fu, Sabareesh Ganapathy, Varghese George, Guei-Yuan Lueh +4 more |
2025-07-01 |
|
| 12333306 |
High performance constant cache and constant access mechanisms |
Subramaniam Maiyuran, Sudarshanram Shetty, Travis T. Schluessler, Guei-Yuan Lueh, PingHang Cheung +3 more |
2025-06-17 |
|
| 12210905 |
Multiple register allocation sizes for threads |
Wei-Yu Chen, Vikranth Vemulapalli, Subramaniam Maiyuran, Jorge Eduardo Parra Osorio, Shuai Mu +2 more |
2025-01-28 |
|
| 12189571 |
Dual pipeline parallel systolic array |
Jorge Parra, Jiasheng Chen, Supratim Pal, Fangwen Fu, Sabareesh Ganapathy +2 more |
2025-01-07 |
|
| 12190158 |
Using sparsity metadata to reduce systolic array power consumption |
Jorge Parra, Supratim Pal, Jiasheng Chen |
2025-01-07 |
|
| 12174783 |
Systolic array of arbitrary physical and logical depth |
Jorge Parra, Wei-Yu Chen, Kaiyu Chen, Varghese George, Junjie Gu +4 more |
2024-12-24 |
$17,261,000 |
| 12093213 |
Computing efficient cross channel operations in parallel computing machines using systolic arrays |
Subramaniam Maiyuran, Jorge Parra, Supratim Pal |
2024-09-17 |
$19,251,000 |
| 12039001 |
Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs |
Subramaniam Maiyuran, Jorge Parra, Supratim Pal, Ashutosh Garg, Shubra Marwaha +3 more |
2024-07-16 |
$26,089,000 |
| 12007935 |
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format |
Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra +3 more |
2024-06-11 |
$21,221,000 |
| 11977885 |
Utilizing structured sparsity in systolic arrays |
Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Chunhui Mei, Durgesh Borkar +10 more |
2024-05-07 |
$26,756,000 |
| 11954063 |
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format |
Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra +3 more |
2024-04-09 |
$27,197,000 |
| 11900502 |
Compiler assisted register file write reduction |
Gang Chen, Subramaniam Maiyuran, Supratim Pal, Ashutosh Garg, Jorge Parra +3 more |
2024-02-13 |
$18,546,000 |
| 11709793 |
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format |
Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra +3 more |
2023-07-25 |
$28,608,000 |
| 11669329 |
Instructions and logic for vector multiply add with zero skipping |
Supratim Pal, Sasikanth Avancha, Ishwar Bhati, Wei-Yu Chen, Dipankar Das +7 more |
2023-06-06 |
$21,341,000 |
| 11669490 |
Computing efficient cross channel operations in parallel computing machines using systolic arrays |
Subramaniam Maiyuran, Jorge Parra, Supratim Pal |
2023-06-06 |
$21,341,000 |
| 11640297 |
Instruction and logic for systolic dot product with accumulate |
Subramaniam Maiyuran, Guei-Yuan Lueh, Supratim Pal, Ashutosh Garg, Jorge Parra +10 more |
2023-05-02 |
$21,235,000 |
| 11636174 |
Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs |
Subramaniam Maiyuran, Jorge Parra, Supratim Pal, Ashutosh Garg, Shubra Marwaha +3 more |
2023-04-25 |
$19,274,000 |
| 11361496 |
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format |
Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra +3 more |
2022-06-14 |
$16,878,000 |
| 11321799 |
Compiler assisted register file write reduction |
Gang Chen, Subramaniam Maiyuran, Supratim Pal, Ashutosh Garg, Jorge Parra +3 more |
2022-05-03 |
$16,346,000 |
| 11314515 |
Instructions and logic for vector multiply add with zero skipping |
Supratim Pal, Sasikanth Avancha, Ishwar Bhati, Wei-Yu Chen, Dipankar Das +7 more |
2022-04-26 |
$25,630,000 |
| 11204977 |
Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs |
Subramaniam Maiyuran, Jorge Parra, Supratim Pal, Ashutosh Garg, Shubra Marwaha +3 more |
2021-12-21 |
$33,282,000 |
| 11182337 |
Computing efficient cross channel operations in parallel computing machines using systolic arrays |
Subramaniam Maiyuran, Jorge Parra, Supratim Pal |
2021-11-23 |
$33,627,000 |
