Issued Patents All Time
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11163578 | Systems and methods for reducing register bank conflicts based on a software hint bit causing a hardware thread switch | Buqi Cheng, Wei-Yu Chen, Guei-Yuan Lueh, Subramaniam Maiyuran | 2021-11-02 |
| 11042370 | Instruction and logic for systolic dot product with accumulate | Subramaniam Maiyuran, Guei-Yuan Lueh, Supratim Pal, Ashutosh Garg, Jorge Parra +10 more | 2021-06-22 |
| 10983581 | Resource load balancing based on usage and power limits | Sanjeev Jahagirdar, Altug Koker, Yoav Harel, Kenneth Brand, Eric Finley +2 more | 2021-04-20 |
| 10983794 | Register sharing mechanism | Guei-Yuan Lueh, Subramaniam Maiyuran, Weiyu Chen, Konrad Trifunovic, Supratim Pal +3 more | 2021-04-20 |
| 10839478 | Accumulator pooling mechanism | Guei-Yuan Lueh, Subramaniam Maiyuran, Wei-Yu Chen, Konrad Trifunovic, Supratim Pal +3 more | 2020-11-17 |
| 10769751 | Single input multiple data processing mechanism | Subramaniam Maiyuran, Jorge F. Garcia Pabon, Vikranth Vemulapalli, Aditya Navale, Saurabh Sharma | 2020-09-08 |
| 10754651 | Register bank conflict reduction for multi-threaded processor | Subramaniam Maiyuran, Buqi Cheng, Ashutosh Garg, Guei-Yuan Lueh, Wei-Yu Chen | 2020-08-25 |
| 10692170 | Software scoreboard information and synchronization | Subramaniam Maiyuran, Supratim Pal, Jorge Parra, Ashwin J. Shivani, Ashutosh Garg +9 more | 2020-06-23 |
| 10417730 | Single input multiple data processing mechanism | Subramaniam Maiyuran, Jorge F. Garcia Pabon, Vikranth Vemulapalli, Aditya Navale, Saurabh Sharma | 2019-09-17 |
| 10360654 | Software scoreboard information and synchronization | Subramaniam Maiyuran, Supratim Pal, Jorge Parra, Ashwin J. Shivani, Ashutosh Garg +9 more | 2019-07-23 |