Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11204977 | Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs | Subramaniam Maiyuran, Supratim Pal, Ashutosh Garg, Shubra Marwaha, Chandra Gurram +3 more | 2021-12-21 |
| 11188618 | Sparse matrix multiplication acceleration mechanism | Subramaniam Maiyuran, Mathew Nevin, Ashutosh Garg, Shubra Marwaha, Shubh Shah | 2021-11-30 |
| 11182337 | Computing efficient cross channel operations in parallel computing machines using systolic arrays | Subramaniam Maiyuran, Supratim Pal, Chandra Gurram | 2021-11-23 |
| 11042370 | Instruction and logic for systolic dot product with accumulate | Subramaniam Maiyuran, Guei-Yuan Lueh, Supratim Pal, Ashutosh Garg, Chandra Gurram +10 more | 2021-06-22 |
| 10983794 | Register sharing mechanism | Guei-Yuan Lueh, Subramaniam Maiyuran, Weiyu Chen, Konrad Trifunovic, Supratim Pal +3 more | 2021-04-20 |
| 10839478 | Accumulator pooling mechanism | Guei-Yuan Lueh, Subramaniam Maiyuran, Wei-Yu Chen, Konrad Trifunovic, Supratim Pal +3 more | 2020-11-17 |
| 10817297 | Method and apparatus for vector-matrix comparison | Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Prasoonkumar Surti, Krishna N. Vinod, Ronen Zohar | 2020-10-27 |
| 10692170 | Software scoreboard information and synchronization | Subramaniam Maiyuran, Supratim Pal, Chandra Gurram, Ashwin J. Shivani, Ashutosh Garg +9 more | 2020-06-23 |
| 10360654 | Software scoreboard information and synchronization | Subramaniam Maiyuran, Supratim Pal, Chandra Gurram, Ashwin J. Shivani, Ashutosh Garg +9 more | 2019-07-23 |
| 9680652 | Dynamic heterogeneous hashing functions in ranges of system memory addressing space | Joydeep Ray, Ramadass Nagarajan | 2017-06-13 |
| 9424209 | Dynamic heterogeneous hashing functions in ranges of system memory addressing space | Joydeep Ray, Ramadass Nagarajan | 2016-08-23 |
| 9032099 | Writeback mechanisms for improving far memory utilization in multi-level memory architectures | Marc Torrant, Joydeep Ray | 2015-05-12 |