Issued Patents All Time
Showing 51–75 of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10699362 | Divergent control flow for fused EUs | Pratik J. Ashar, Kaiyu Chen, Subramaniam Maiyuran, Brent A. Schwartz, Darin Starkey | 2020-06-30 |
| 10691430 | Latency scheduling mehanism | Wei-Hao Pan, Wei-Yu Chen | 2020-06-23 |
| 10692170 | Software scoreboard information and synchronization | Subramaniam Maiyuran, Supratim Pal, Jorge Parra, Chandra Gurram, Ashwin J. Shivani +9 more | 2020-06-23 |
| 10649956 | Engine to enable high speed context switching via on-die storage | Altug Koker, Prasoonkumar Surti, David Puffer, Subramaniam Maiyuran, Abhishek R. Appu +7 more | 2020-05-12 |
| 10636112 | Graphics processor register data re-use mechanism | Slawomir Grajewski, Kaiyu Chen, Subramaniam Maiyuran | 2020-04-28 |
| 10599571 | Instruction prefetch mechanism | Vasileios Porpodas, Subramaniam Maiyuran, Wei-Yu Chen | 2020-03-24 |
| 10593011 | Methods and apparatus to support dynamic adjustment of graphics processing unit frequency | Lei Shen, Yong Jiang | 2020-03-17 |
| 10565675 | Intelligent graphics dispatching mechanism | Balaji Vembu, Murali Ramadoss, Subramaniam Maiyuran, Abhishek R. Appu, Joydeep Ray +4 more | 2020-02-18 |
| 10565676 | Thread prefetch mechanism | Adam T. Lake, Balaji Vembu, Murali Ramadoss, Prasoonkumar Surti, Abhishek R. Appu +8 more | 2020-02-18 |
| 10565670 | Graphics processor register renaming mechanism | Kaiyu Chen, Subramaniam Maiyuran | 2020-02-18 |
| 10552211 | Mechanism to increase thread parallelism in a graphics processor | Yuting Yang, Yuenian Yang, Julia A. Gould | 2020-02-04 |
| 10521271 | Hybrid low power homogenous grapics processing units | Abhishek R. Appu, Altug Koker, Balaji Vembu, Joydeep Ray, Kamal Sinha +16 more | 2019-12-31 |
| 10453427 | Register spill/fill using shared local memory space | Joydeep Ray, Altug Koker, Balaji Vembu, Murali Ramadoss, James Valerio +7 more | 2019-10-22 |
| 10430229 | Multiple-patch SIMD dispatch mode for domain shaders | Jayashree Venkatesh, Subramaniam Maiyuran | 2019-10-01 |
| 10423415 | Hierarchical general register file (GRF) for execution block | Abhishek R. Appu, Altug Koker, Joydeep Ray, Kamal Sinha, Kiran C. Veernapu +7 more | 2019-09-24 |
| 10373288 | Transpose of image data between a linear and a Y-tiled storage format | Yuting Yang, Lei Shen, John R. Hartwig, Kin-Hang Cheung | 2019-08-06 |
| 10360654 | Software scoreboard information and synchronization | Subramaniam Maiyuran, Supratim Pal, Jorge Parra, Chandra Gurram, Ashwin J. Shivani +9 more | 2019-07-23 |
| 10318292 | Hardware instruction set to replace a plurality of atomic operations with a single atomic operation | Satyajit Sarangi, Thomas Raoux, Subramaniam Maiyuran | 2019-06-11 |
| 10282227 | Efficient preemption for graphics processors | Subramaniam Maiyuran, Wei-Yu Chen, Kaiyu Chen | 2019-05-07 |
| 10282812 | Page faulting and selective preemption | Altug Koker, Ingo Wald, David Puffer, Subramaniam Maiyuran, Prasoonkumar Surti +4 more | 2019-05-07 |
| 10235736 | Intelligent graphics dispatching mechanism | Balaji Vembu, Murali Ramadoss, Subramaniam Maiyuran, Abhishek R. Appu, Joydeep Ray +4 more | 2019-03-19 |
| 10191724 | Compiler-based instruction scoreboarding | Bu Qi Cheng, Wei-Yu Chen | 2019-01-29 |
| 9886734 | Techniques for graphics data prefetching | Wei-Yu Chen, Subramaniam Maiyuran | 2018-02-06 |
| 9880839 | Instruction that performs a scatter write | Wei-Yu Chen, Subramaniam Maiyuran, Supratim Pal | 2018-01-30 |
| 9832247 | Processing video data in a cloud | Zhiwei Ying, Changliang Wang | 2017-11-28 |