Issued Patents All Time
Showing 25 most recent of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12189523 | Command-differentiated storage of internally and externally sourced data | Thomas J. Sheffler, Lawrence Lai, Liang Ping Peng | 2025-01-07 |
| 12182036 | Providing content-aware cache replacement and insertion policies in processor-based devices | George Patsilaras, Engin Ipek, Goran Goran, Hamza Omar, Jeffrey Gemar +2 more | 2024-12-31 |
| 12093155 | Allocation of data sub-tensors onto hardware sub-arrays | Hee Jun Park, Niraj Shantilal PALIWAL | 2024-09-17 |
| 11748252 | Data write from pre-programmed register | Thomas J. Sheffler, Lawrence Lai, Liang Ping Peng | 2023-09-05 |
| 11720485 | DRAM with command-differentiated storage of internally and externally sourced data | Thomas J. Sheffler, Lawrence Lai, Liang Ping Peng | 2023-08-08 |
| 11681624 | Space and time cache coherency | Andrew E. Turner, George Patsilaras | 2023-06-20 |
| 11636057 | Data re-encoding for energy-efficient data transfer in a computing device | Engin Ipek, George Patsilaras, Prajakt Kulkarni, Can Hankendi, Fahad Ali +2 more | 2023-04-25 |
| 11256894 | Multi-stage biometric authentication | Wesley James HOLLAND, Rashmi Kulkarni, Ling Feng Huang, Huang-Chou Huang, Jeffrey Shabel +4 more | 2022-02-22 |
| 11204863 | Memory component that performs data write from pre-programmed register | Thomas J. Sheffler, Lawrence Lai, Liang Ping Peng | 2021-12-21 |
| 11016898 | System and method for mixed tile-aware and tile-unaware traffic through a tile-based address aperture | Andrew E. Turner, George Patsilaras, Wesley James HOLLAND, Jeffrey Shabel, Simon Peter William Booth | 2021-05-25 |
| 10747671 | System and method for intelligent tile-based prefetching of image frames in a system on a chip | Wesley James HOLLAND, Andrew E. Turner, George Patsilaras, Jeffrey Shabel, Simon Peter William Booth | 2020-08-18 |
| 10592292 | Method and apparatus for optimized execution using resource utilization maps | Mehrdad Mohammad H. Reshadi, Babak Salamat, Gheorghe C. Cascaval, Mark S. Fowler, Andrey Ermolinskiy | 2020-03-17 |
| 10552310 | Single command, multiple column-operation memory device | Thomas J. Sheffler, Lawrence Lai, Liang Ping Peng | 2020-02-04 |
| 10503643 | Cache coherence with functional address apertures | Wesley James HOLLAND, Hao Liu, Andrew E. Turner | 2019-12-10 |
| 10386904 | Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks | Jason Edward Podaima, Christophe Avoinne, Manokanthan Somasundaram, Sina Dena, Paul Christopher John Wiercienski +4 more | 2019-08-20 |
| 10339058 | Automatic cache coherency for page table data | Andrew E. Turner, Farrukh HIJAZ | 2019-07-02 |
| 10338837 | Dynamic mapping of applications on NVRAM/DRAM hybrid memory | Subrato Kumar De, Dexter Tamio Chun, Yanru Li, Richard Alan Stewart | 2019-07-02 |
| 10261910 | Cache line compaction of compressed data segments | Andrew E. Turner, George Patsilaras | 2019-04-16 |
| 10255181 | Dynamic input/output coherency | Andrew E. Turner | 2019-04-09 |
| 10248565 | Hybrid input/output coherent write | Andrew E. Turner | 2019-04-02 |
| 10114585 | Transaction elimination using metadata | Jeffrey Hao Chu, Subrato Kumar De, Dexter Tamio Chun, Richard Alan Stewart | 2018-10-30 |
| 9910799 | Interconnect distributed virtual memory (DVM) message preemptive responding | Christophe Avoinne, Jason Edward Podaima, Manokanthan Somasundaram, Thomas Zeng, Jaya Prakash Subramaniam Ganasan +1 more | 2018-03-06 |
| 9898400 | Single command, multiple column-operation memory device | Thomas A. Sheffler, Lawrence Lai, Liang Ping Peng | 2018-02-20 |
| 9858196 | Power aware padding | George Patsilaras, Ali Iranli, Andrew E. Turner | 2018-01-02 |
| 9846612 | Systems and methods of memory bit flip identification for debugging and power management | Madan Krishnappa, Chinh Tran, Li Zhang, Alan Robert Young, William John Bainbridge | 2017-12-19 |