| 12182016 |
Memory circuit with power registers |
Matthew B. Smittle |
2024-12-31 |
$93,374,000 |
| 12141474 |
Queue circuit for controlling access to a memory circuit |
Matthew B. Smittle |
2024-11-12 |
$141,070,000 |
| 11983538 |
Load-store unit dual tags and replays |
Ajay Anant Ingle |
2024-05-14 |
$430,599,000 |
| 11960400 |
Managing multiple cache memory circuit operations |
Matthew B. Smittle |
2024-04-16 |
$205,776,000 |
| 11740973 |
Instruction error handling |
Matthew B. Smittle, Jama I. Barreh |
2023-08-29 |
$189,344,000 |
| 11656876 |
Removal of dependent instructions from an execution pipeline |
Deepak Panwar |
2023-05-23 |
$368,108,000 |
| 11537505 |
Forced debug mode entry |
Matthew B. Smittle |
2022-12-27 |
$136,955,000 |
| 11531550 |
Program thread selection between a plurality of execution pipelines |
Christopher H. Olson |
2022-12-20 |
$137,057,000 |
| 11507414 |
Circuit for fast interrupt handling |
Thomas M. Wicki, Jama I. Barreh |
2022-11-22 |
$97,812,000 |
| 11126577 |
Distributed fairness protocol for interconnect networks |
Manish K. Shah, Mark Luttrell |
2021-09-21 |
$104,189,000 |
| 11119149 |
Debug command execution using existing datapath circuitry |
Deepak Panwar, Muhammad Tauseef Rab, Matthew B. Smittle |
2021-09-14 |
$45,453,000 |
| 11086631 |
Illegal instruction exception handling |
Matthew B. Smittle |
2021-08-10 |
$7,704,000 |
| 11023342 |
Cache diagnostic techniques |
Jama I. Barreh, Thomas M. Wicki, Matthew B. Smittle |
2021-06-01 |
$43,254,000 |
| 10860326 |
Multi-threaded instruction buffer design |
Jama I. Barreh, Manish K. Shah |
2020-12-08 |
$48,597,000 |
| 10534606 |
Run-length encoding decompression |
Jeffrey S. Brooks, Albert Danysh, Shasank K. Chavan, Prateek Agrawal, Andrew T. Ewoldt +1 more |
2020-01-14 |
$41,845,000 |
| 10474601 |
Distributed fairness protocol for interconnect networks |
Manish K. Shah, Mark Luttrell |
2019-11-12 |
$62,387,000 |
| 10430342 |
Optimizing thread selection at fetch, select, and commit stages of processor core pipeline |
Yuan C. Chou, Gideon N. Levinsky, Manish K. Shah, Matthew B. Smittle |
2019-10-01 |
$38,892,000 |
| 10346173 |
Multi-threaded instruction buffer design |
Jama I. Barreh, Manish K. Shah |
2019-07-09 |
$30,255,000 |
| 9710042 |
Adaptive microprocessor power ramp control |
Haowei Zhang, Xiaoying Shen, Sebastian Turullols |
2017-07-18 |
$65,228,000 |
| 9690625 |
System and method for out-of-order resource allocation and deallocation in a threaded machine |
— |
2017-06-27 |
$29,850,000 |
| 9672298 |
Precise excecution of versioned store instructions |
Zoran Radovic, Jared C. Smolens, Paul J. Jordan, Mark Luttrell |
2017-06-06 |
$31,119,000 |
| 9665375 |
Mitigation of thread hogs on a threaded processor and prevention of allocation of resources to one or more instructions following a load miss |
Yuan C. Chou, Mark Luttrell |
2017-05-30 |
$27,102,000 |
| 9304767 |
Single cycle data movement between general purpose and floating-point registers |
Christopher H. Olson, Jeffrey S. Brooks |
2016-04-05 |
$46,575,000 |
| 9286075 |
Optimal deallocation of instructions from a unified pick queue |
Matthew B. Smittle |
2016-03-15 |
$71,190,000 |
| 9262171 |
Dependency matrix for the determination of load dependencies |
Matthew B. Smittle, Xiang Li |
2016-02-16 |
$36,803,000 |
