Issued Patents All Time
Showing 26–50 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9122487 | System and method for balancing instruction loads between multiple execution units using assignment history | Gregory F. Grohoski | 2015-09-01 |
| 9058180 | Unified high-frequency out-of-order pick queue with support for triggering early issue of speculative instructions | Matthew B. Smittle, Mark Luttrell, Xiang Li | 2015-06-16 |
| 8904156 | Perceptron-based branch prediction mechanism for predicting conditional branch instructions on a multithreaded processor | Manish K. Shah, Gregory F. Grohoski, Jama I. Barreh | 2014-12-02 |
| 8832464 | Processor and method for implementing instruction support for hash algorithms | Christopher H. Olson, Jeffrey S. Brooks | 2014-09-09 |
| 8769246 | Mechanism for selecting instructions for execution in a multithreaded processor | — | 2014-07-01 |
| 8560814 | Thread fairness on a multi-threaded processor with multi-cycle cryptographic operations | Christopher H. Olson, Gregory F. Grohoski | 2013-10-15 |
| 8504805 | Processor operating mode for mitigating dependency conditions between instructions having different operand sizes | Paul J. Jordan, Jama I. Barreh, Matthew B. Smittle, Yuan C. Chou, Jared C. Smolens | 2013-08-06 |
| 8458446 | Accessing a multibank register file using a thread identifier | Christopher H. Olson, Xiang Li | 2013-06-04 |
| 8438208 | Processor and method for implementing instruction support for multiplication of large operands | Christopher H. Olson, Jeffrey S. Brooks, Paul J. Jordan | 2013-05-07 |
| 8429386 | Dynamic tag allocation in a multithreaded out-of-order processor | Paul J. Jordan, Jama I. Barreh | 2013-04-23 |
| 8356185 | Apparatus and method for local operand bypassing for cryptographic instructions | Christopher H. Olson, Gregory F. Grohoski | 2013-01-15 |
| 8347309 | Dynamic mitigation of thread hogs on a threaded processor | Jared C. Smolens, Matthew B. Smittle | 2013-01-01 |
| 8335912 | Logical map table for detecting dependency conditions between instructions having varying width operand values | Jama I. Barreh, Jeffrey S. Brooks, Howard Levy | 2012-12-18 |
| 8335911 | Dynamic allocation of resources in a threaded, heterogeneous processor | Gregory F. Grohoski | 2012-12-18 |
| 8301865 | System and method to manage address translation requests | Gregory F. Grohoski, Paul J. Jordan, Mark Luttrell, Zeid H. Samoail | 2012-10-30 |
| 8225034 | Hybrid instruction buffer | Yue Chang, Jama I. Barreh | 2012-07-17 |
| 8195921 | Method and apparatus for decoding multithreaded instructions of a microprocessor | Manish K. Shah | 2012-06-05 |
| 8195919 | Handling multi-cycle integer operations for a multi-threaded processor | Christopher H. Olson, Manish K. Shah, Jeffrey S. Brooks | 2012-06-05 |
| 8195923 | Methods and mechanisms to support multiple features for a number of opcodes | Lawrence Spracklen, Gregory F. Grohoski, Christopher H. Olson | 2012-06-05 |
| 8099586 | Branch misprediction recovery mechanism for microprocessors | Yuan C. Chou, Mark Luttrell, Paul J. Jordan, Manish K. Shah | 2012-01-17 |
| 8095778 | Method and system for sharing functional units of a multithreaded processor | — | 2012-01-10 |
| 7941642 | Method for selecting between divide instructions associated with respective threads in a multi-threaded processor | Jeffrey S. Brooks, Christopher H. Olson | 2011-05-10 |
| 7890734 | Mechanism for selecting instructions for execution in a multithreaded processor | — | 2011-02-15 |
| 7861063 | Delay slot handling in a processor | Paul J. Jordan, Jama I. Barreh | 2010-12-28 |
| 7778105 | Memory with write port configured for double pump write | Xiang Li | 2010-08-17 |