Issued Patents All Time
Showing 51–75 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7747771 | Register access protocol in a multihreaded multi-core processor | Manish K. Shah, Mark Luttrell, Gregory F. Grohoski | 2010-06-29 |
| 7533248 | Multithreaded processor including a functional unit shared between multiple requestors and arbitration therefor | Gregory F. Grohoski | 2009-05-12 |
| 7523330 | Thread-based clock enabling in a multi-threaded processor | Jeffrey S. Brooks, Christopher H. Olson | 2009-04-21 |
| 7519796 | Efficient utilization of a store buffer using counters | Mark Luttrell | 2009-04-14 |
| 7509484 | Handling cache misses by selectively flushing the pipeline | Mark Luttrell | 2009-03-24 |
| 7478225 | Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor | Jeffrey S. Brooks, Christopher H. Olson | 2009-01-13 |
| 7426630 | Arbitration of window swap operations | Jike Chong, Paul J. Jordan | 2008-09-16 |
| 7401206 | Apparatus and method for fine-grained multithreading in a multipipelined processor core | Ricky C. Hetherington, Gregory F. Grohoski | 2008-07-15 |
| 7383403 | Concurrent bypass to instruction buffers in a fine grain multithreaded processor | Jama I. Barreh, Manish K. Shah | 2008-06-03 |
| 7350053 | Software accessible fast VA to PA translation | Rabin Sugumar, Paul J. Jordan | 2008-03-25 |
| 7343474 | Minimal address state in a fine grain multithreaded processor | Paul J. Jordan, Jama I. Barreh | 2008-03-11 |
| 7330988 | Method and apparatus for power throttling in a multi-thread processor | Ricky C. Hetherington | 2008-02-12 |
| 7216216 | Register window management using first pipeline to change current window and second pipeline to read operand from old window and write operand to new window | Christopher H. Olson, Jeffrey S. Brooks | 2007-05-08 |
| 7185178 | Fetch speculation in a multithreaded processor | Jama I. Barreh | 2007-02-27 |
| 5943494 | Method and system for processing multiple branch instructions that write to count and link registers | Christopher H. Olson | 1999-08-24 |
| 5898864 | Method and system for executing a context-altering instruction without performing a context-synchronization operation within high-performance processors | James Allan Kahle, Albert J. Loper, Soummya Mallick | 1999-04-27 |
| 5880983 | Floating point split multiply/add system which has infinite precision | Timothy A. Elliott, Christopher H. Olson, Terence M. Potter | 1999-03-09 |
| 5815406 | Method and system for designing a circuit using RC and timing weighting of nets | Christopher H. Olson | 1998-09-29 |
| 5809323 | Method and apparatus for executing fixed-point instructions within idle execution units of a superscalar processor | Lee Evan Eisen, Soummya Mallick, Sung Ho Park, Rajesh B. Patel, Michael Putrino | 1998-09-15 |
| 5802346 | Method and system for minimizing the delay in executing branch-on-register instructions | Christopher H. Olson | 1998-09-01 |
| 5794024 | Method and system for dynamically recovering a register-address-table upon occurrence of an interrupt or branch misprediction | Thomas Hoy, Christopher H. Olson, Terence M. Potter, Thomas L. Thomas, Jr. | 1998-08-11 |
| 5790445 | Method and system for performing a high speed floating point add operation | Lee Evan Eisen, Timothy A. Elliott, Christopher H. Olson | 1998-08-04 |
| 5717587 | Method and system for recording noneffective instructions within a data processing system | Bryan Black, Marvin Denman, Lee Evan Eisen, Albert J. Loper, Soummya Mallick +1 more | 1998-02-10 |
| 5678016 | Processor and method for managing execution of an instruction which determine subsequent to dispatch if an instruction is subject to serialization | Lee Evan Eisen, Christopher H. Olson, Michael Putrino | 1997-10-14 |
| 5634103 | Method and system for minimizing branch misprediction penalties within a processor | Carl Dietz, Christopher H. Olson | 1997-05-27 |