Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11740973 | Instruction error handling | Matthew B. Smittle, Robert T. Golla | 2023-08-29 |
| 11507414 | Circuit for fast interrupt handling | Robert T. Golla, Thomas M. Wicki | 2022-11-22 |
| 11023342 | Cache diagnostic techniques | Robert T. Golla, Thomas M. Wicki, Matthew B. Smittle | 2021-06-01 |
| 10860326 | Multi-threaded instruction buffer design | Robert T. Golla, Manish K. Shah | 2020-12-08 |
| 10346173 | Multi-threaded instruction buffer design | Robert T. Golla, Manish K. Shah | 2019-07-09 |
| 9529594 | Miss buffer for a multi-threaded processor | Manish K. Shah | 2016-12-27 |
| 8904156 | Perceptron-based branch prediction mechanism for predicting conditional branch instructions on a multithreaded processor | Manish K. Shah, Gregory F. Grohoski, Robert T. Golla | 2014-12-02 |
| 8555038 | Processor and method providing instruction support for instructions that utilize multiple register windows | Christopher H. Olson, Paul J. Jordan | 2013-10-08 |
| 8504805 | Processor operating mode for mitigating dependency conditions between instructions having different operand sizes | Robert T. Golla, Paul J. Jordan, Matthew B. Smittle, Yuan C. Chou, Jared C. Smolens | 2013-08-06 |
| 8429386 | Dynamic tag allocation in a multithreaded out-of-order processor | Paul J. Jordan, Robert T. Golla | 2013-04-23 |
| 8335912 | Logical map table for detecting dependency conditions between instructions having varying width operand values | Robert T. Golla, Jeffrey S. Brooks, Howard Levy | 2012-12-18 |
| 8225034 | Hybrid instruction buffer | Robert T. Golla, Yue Chang | 2012-07-17 |
| 8037250 | Arbitrating cache misses in a multithreaded/multi-core processor | Manish K. Shah | 2011-10-11 |
| 7861063 | Delay slot handling in a processor | Robert T. Golla, Paul J. Jordan | 2010-12-28 |
| 7434000 | Handling duplicate cache misses in a multithreaded/multi-core processor | Manish K. Shah | 2008-10-07 |
| 7383403 | Concurrent bypass to instruction buffers in a fine grain multithreaded processor | Manish K. Shah, Robert T. Golla | 2008-06-03 |
| 7353445 | Cache error handling in a multithreaded/multi-core processor | Manish K. Shah | 2008-04-01 |
| 7343474 | Minimal address state in a fine grain multithreaded processor | Paul J. Jordan, Robert T. Golla | 2008-03-11 |
| 7185178 | Fetch speculation in a multithreaded processor | Robert T. Golla | 2007-02-27 |