TW

Thomas M. Wicki

Oracle: 16 patents #615 of 14,854Top 5%
Fujitsu Limited: 9 patents #3,538 of 24,456Top 15%
CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
HS Hal Computer Systems: 1 patents #17 of 34Top 50%
WT Western Digital Technologies: 1 patents #1,787 of 3,180Top 60%
Overall (All Time): #137,789 of 4,157,543Top 4%
28
Patents All Time

Issued Patents All Time

Showing 25 most recent of 28 patents

Patent #TitleCo-InventorsDate
11507414 Circuit for fast interrupt handling Robert T. Golla, Jama I. Barreh 2022-11-22
11023342 Cache diagnostic techniques Jama I. Barreh, Robert T. Golla, Matthew B. Smittle 2021-06-01
10387314 Reducing cache coherence directory bandwidth by aggregating victimization requests Jurgen Schulz, Paul N. Loewenstein 2019-08-20
10007629 Inter-processor bus link and switch chip failure recovery David Richard Smentek, Sumti Jairath, Kathirgamar Aingaran, Ali Vahidsafa, Paul N. Loewenstein 2018-06-26
9921899 Monitoring serial link errors Michelle Wong, Dawei Huang, Albert Martin 2018-03-20
9285865 Dynamic link scaling based on bandwidth utilization Brian F. Keish, Sebastian Turullols 2016-03-15
9135175 Distributed cache coherency directory with failure redundancy Stephen E. Phillips, Nicholas E. Aneshansley, Ramaswamy Sivaramakrishnan, Paul N. Loewenstein 2015-09-15
7609092 Automatic phase-detection circuit for clocks with known ratios Bharat Daga 2009-10-27
7523342 Data and control integrity for transactions in a computer system Peter Fu 2009-04-21
7366843 Computer system implementing synchronized broadcast using timestamps Robert E. Cypher, David A. Wood, Mark D. Hill 2008-04-29
6912628 N-way set-associative external cache with standard DDR memory devices Koen Bennebroek 2005-06-28
6832294 Interleaved n-way set-associative external cache Koen Bennebroek 2004-12-14
6684299 Method for operating a non-blocking hierarchical cache throttle Ricky C. Hetherington 2004-01-27
6393023 System and method for acknowledging receipt of messages within a packet based communication network Takeshi Shimizu, Wolf-Dietrich Weber, Patrick James Helland, Winfried W. Wilcke 2002-05-21
6269426 Method for operating a non-blocking hierarchical cache throttle Ricky C. Hetherington 2001-07-31
6212602 Cache tag caching Meera Kasinathan, Ricky C. Hetherington 2001-04-03
6154815 Non-blocking hierarchical cache throttle Ricky C. Hetherington 2000-11-28
6122709 Cache with reduced tag information storage Meera Kasinathan, Ricky C. Hetherington 2000-09-19
6119205 Speculative cache line write backs to avoid hotspots Meera Kasinathan, Fong Pong, Ricky C. Hetherington 2000-09-12
6003064 System and method for controlling data transmission between network elements Patrick James Helland, Jeffrey D. Larson, Albert Mu, Raghu Sastry, Richard L. Schober 1999-12-14
5987629 Interconnect fault detection and localization method and apparatus Raghu Sastry, Jeffrey D. Larson, Albert Mu, John R. Slice, Richard L. Schober 1999-11-16
5959995 Asynchronous packet switching Patrick James Helland, Takeshi Shimizu, Wolf-Dietrich Weber, Winfried W. Wilcke 1999-09-28
5931967 Method and apparatus for detection of errors in multiple-word communications Takeshi Shimizu, Patrick James Helland 1999-08-03
5892766 Method and apparatus for coordinating access to an output of a routing device in a packet switching network Jeffrey D. Larson, Albert Mu 1999-04-06
5838684 Low latency, high clock frequency plesioasynchronous packet-based crossbar switching chip system and method Jeffrey D. Larson, Albert Mu, Raghu Sastry 1998-11-17