Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12277041 | Method for migrating CPU state from an inoperable core to a spare core | James M. Lewis, Paul J. Jordan, Gregory Onufer | 2025-04-15 |
| 11709742 | Method for migrating CPU state from an inoperable core to a spare core | James M. Lewis, Paul J. Jordan, Gregory Onufer | 2023-07-25 |
| 11263012 | Method for migrating CPU state from an inoperable core to a spare core | James M. Lewis, Paul J. Jordan, Gregory Onufer | 2022-03-01 |
| 10656205 | Narrow-parallel scan-based device testing | Mark Semmelmeyer, Sebastian Turullols, Scott Cooke, Senthilkumar Diraviam, Preethi Sama | 2020-05-19 |
| 10528351 | Method for migrating CPU state from an inoperable core to a spare core | James M. Lewis, Paul J. Jordan, Gregory Onufer | 2020-01-07 |
| 10467139 | Fault-tolerant cache coherence over a lossy network | Paul N. Loewenstein, Damien Walker, Priyambada Mitra, Matthew Cohen, Josephus C. Ebergen +1 more | 2019-11-05 |
| 10452547 | Fault-tolerant cache coherence over a lossy network | Paul N. Loewenstein, Damien Walker, Priyambada Mitra, Matthew Cohen, Josephus C. Ebergen +1 more | 2019-10-22 |
| 10248520 | High speed functional test vectors in low power test conditions of a digital integrated circuit | — | 2019-04-02 |
| 10073139 | Cycle deterministic functional testing of a chip with asynchronous clock domains | Sriram Anandakumar | 2018-09-11 |
| 10007629 | Inter-processor bus link and switch chip failure recovery | Thomas M. Wicki, David Richard Smentek, Sumti Jairath, Kathirgamar Aingaran, Paul N. Loewenstein | 2018-06-26 |
| 9864604 | Distributed mechanism for clock and reset control in a microprocessor | — | 2018-01-09 |
| 9746876 | Drift compensation for a real time clock circuit | — | 2017-08-29 |
| 9710273 | Method for migrating CPU state from an inoperable core to a spare core | James M. Lewis, Paul J. Jordan, Gregory Onufer | 2017-07-18 |
| 9645903 | Managing failed memory modules | Connie W. Cheung | 2017-05-09 |
| 9632141 | Simultaneous transition testing of different clock domains in a digital integrated circuit | Roger Charles Mistely | 2017-04-25 |
| 9569322 | Memory migration in presence of live memory traffic | Connie W. Cheung | 2017-02-14 |
| 9509317 | Rotational synchronizer circuit for metastablity resolution | Robert P. Masleid | 2016-11-29 |
| 9460013 | Method and system for removal of a cache agent | David Richard Smentek, Venkatram Krishnaswamy, Thirumalai Swamy Suresh | 2016-10-04 |
| 9404967 | Mixing of low speed and high speed clocks to improve test precision of a digital integrated circuit | — | 2016-08-02 |
| 9355211 | Unified tool for automatic design constraints generation and verification | Yibin Xia, Dinesh R. AMIRTHARAJ, Alan Smith, Senthilkumar Diraviam, Mohd Jamil Mohd | 2016-05-31 |
| 9323600 | Systems and methods for retiring and unretiring cache lines | Ramaswamy Sivaramakrishnan, Aaron S. Wynn, Connie W. Cheung | 2016-04-26 |
| 9218018 | Method and apparatus for distributed generation of multiple configurable ratioed clock domains within a high speed domain | Robert P. Masleid | 2015-12-22 |
| 9052911 | Mechanism for consistent core hang detection in a a processor core | Chih Heng Liu | 2015-06-09 |
| 9026705 | Interrupt processing unit for preventing interrupt loss | John R. Feehrer, Fred Tsai, Sumti Jairath | 2015-05-05 |
| 9015460 | Hybrid hardwired/programmable reset sequence controller | — | 2015-04-21 |