Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9355211 | Unified tool for automatic design constraints generation and verification | Dinesh R. AMIRTHARAJ, Ali Vahidsafa, Alan Smith, Senthilkumar Diraviam, Mohd Jamil Mohd | 2016-05-31 |
| 8751983 | Method for design partitioning at the behavioral circuit design level | Thomas A. Mitchell, Krishnan Sundaresan, Quan Tran | 2014-06-10 |
| 7861200 | Setup and hold time characterization device and method | Yifeng Yang, Yun Zhang, David J. Chapman | 2010-12-28 |