Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11961575 | Single “A” latch with an array of “B” latches | Thomas A. Ziaja, Uma Durairajan | 2024-04-16 |
| 11449404 | Built-in self-test for processor unit with combined memory and logic | Thomas A. Ziaja | 2022-09-20 |
| 11443822 | Method and circuit for row scannable latch array | Thomas A. Ziaja, Uma Durairajan | 2022-09-13 |
| 11443823 | Method and circuit for scan dump of latch array | Thomas A. Ziaja, Uma Durairajan | 2022-09-13 |
| 11428737 | Array of processor units with local BIST | Thomas A. Ziaja | 2022-08-30 |
| 9355211 | Unified tool for automatic design constraints generation and verification | Yibin Xia, Ali Vahidsafa, Alan Smith, Senthilkumar Diraviam, Mohd Jamil Mohd | 2016-05-31 |