| 12243604 |
Scannable memory array and a method for scanning memory |
Paul J. Jordan |
2025-03-04 |
| 11961575 |
Single “A” latch with an array of “B” latches |
Uma Durairajan, Dinesh R. AMIRTHARAJ |
2024-04-16 |
| 11449404 |
Built-in self-test for processor unit with combined memory and logic |
Dinesh R. AMIRTHARAJ |
2022-09-20 |
| 11443822 |
Method and circuit for row scannable latch array |
Uma Durairajan, Dinesh R. AMIRTHARAJ |
2022-09-13 |
| 11443823 |
Method and circuit for scan dump of latch array |
Uma Durairajan, Dinesh R. AMIRTHARAJ |
2022-09-13 |
| 11428737 |
Array of processor units with local BIST |
Dinesh R. AMIRTHARAJ |
2022-08-30 |
| 10408876 |
Memory circuit march testing |
Lancelot Kwong |
2019-09-10 |
| 9401223 |
At-speed test of memory arrays using scan |
Murali M. R. Gala |
2016-07-26 |
| 8214703 |
Testing multi-core processors |
Murali M. R. Gala, Olivier Caty, Paul J. Dickinson |
2012-07-03 |
| 8074133 |
Method and apparatus for testing delay faults |
Kevin D. Woodling, Robert F. Molyneaux |
2011-12-06 |
| 8065572 |
At-speed scan testing of memory arrays |
Murali M. R. Gala, Paul J. Dickinson, Karl P. Dahlgren, David L. Curwen, Oliver Caty +3 more |
2011-11-22 |
| 7795899 |
Enabling on-chip features via efuses |
Gregory F. Grohoski, Christopher H. Olson, Lawrence Spracklen |
2010-09-14 |
| 7657805 |
Integrated circuit with blocking pin to coordinate entry into test mode |
Kevin D. Woodling, Robert F. Molyneaux |
2010-02-02 |
| 7657807 |
Integrated circuit with embedded test functionality |
Daniel Watkins, Hunter S. Donahue |
2010-02-02 |
| 6813201 |
Automatic generation and validation of memory test models |
Kamran Zarrineh, Amitava Majumdar |
2004-11-02 |
