Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8074133 | Method and apparatus for testing delay faults | Thomas A. Ziaja, Robert F. Molyneaux | 2011-12-06 |
| 7657805 | Integrated circuit with blocking pin to coordinate entry into test mode | Thomas A. Ziaja, Robert F. Molyneaux | 2010-02-02 |
| 7574581 | Cross-chip communication mechanism in distributed node topology to access free-running scan registers in clock-controlled components | Michael Stephen Floyd, Larry Scott Leitner, Kevin F. Reick | 2009-08-11 |