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Address translation cache invalidation in a microprocessor |
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Processor with resource usage counters for per-thread accounting |
William J. Armstrong, Michael Stephen Floyd, Ronald Nick Kalla, Balaram Sinharoy |
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Processor core with per-thread resource usage accounting logic |
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Intelligent SMT thread hang detect taking into account shared resource contention/blocking |
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Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (SMT) processor |
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Method to operate cache-inhibited memory mapped commands to access registers |
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Intelligent SMT thread hang detect taking into account shared resource contention/blocking |
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