Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11301392 | Address translation cache invalidation in a microprocessor | Debapriya Chatterjee, Bryant Cockcroft, John A. Schumann, Karen Yokum | 2022-04-12 |
| 11243864 | Identifying translation errors | Bryant Cockcroft, John A. Schumann, Debapriya Chatterjee, Kevin Barnett, Karen Yokum | 2022-02-08 |
| 11080122 | Software-invisible interrupt for a microprocessor | John A. Schumann, Debapriya Chatterjee, Wallace Sharp, Bryant Cockcroft | 2021-08-03 |
| 10915456 | Address translation cache invalidation in a microprocessor | Debapriya Chatterjee, Bryant Cockcroft, John A. Schumann, Karen Yokum | 2021-02-09 |
| 9003417 | Processor with resource usage counters for per-thread accounting | William J. Armstrong, Michael Stephen Floyd, Ronald Nick Kalla, Balaram Sinharoy | 2015-04-07 |
| 8639855 | Information collection and storage for single core chips to 'N core chips | Michael W. Harper, Mack W. Riley | 2014-01-28 |
| 8271738 | Apparatus for operating cache-inhibited memory mapped commands to access registers | James Stephen Fields, Jr., Michael Stephen Floys, Paul Frank Lecocq, Kevin F. Reick | 2012-09-18 |
| 8209698 | Processor core with per-thread resource usage accounting logic | William J. Armstrong, Michael Stephen Floyd, Ronald Nick Kalla, Balaram Sinharoy | 2012-06-26 |
| 7996703 | Method and apparatus to avoid power transients during a microprocessor test | Michael Stephen Floyd, Norman K. James, Jeffrey William Kellington | 2011-08-09 |
| 7725685 | Intelligent SMT thread hang detect taking into account shared resource contention/blocking | Michael Stephen Floyd | 2010-05-25 |
| 7657893 | Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (SMT) processor | William J. Armstrong, Michael Stephen Floyd, Ronald Nick Kalla, Balaram Sinharoy | 2010-02-02 |
| 7574581 | Cross-chip communication mechanism in distributed node topology to access free-running scan registers in clock-controlled components | Michael Stephen Floyd, Kevin F. Reick, Kevin D. Woodling | 2009-08-11 |
| 7392350 | Method to operate cache-inhibited memory mapped commands to access registers | James Stephen Fields, Jr., Michael Stephen Floyd, Paul Frank Lecocq, Kevin F. Reick | 2008-06-24 |
| 7343476 | Intelligent SMT thread hang detect taking into account shared resource contention/blocking | Michael Stephen Floyd | 2008-03-11 |
| 6857083 | Method and system for triggering a debugging unit | Michael Stephen Floyd, Paul J. Jordan | 2005-02-15 |
| 6802031 | Method and apparatus for increasing the effectiveness of system debug and analysis | Michael Stephen Floyd, Kevin F. Reick | 2004-10-05 |
| 6633838 | Multi-state logic analyzer integral to a microprocessor | Lakshminarayana B. Arimilli, Michael Stephen Floyd, Kevin F. Reick, Jennifer L. Vargus | 2003-10-14 |
| 6543003 | Method and apparatus for multi-stage hang recovery in an out-of-order microprocessor | Michael Stephen Floyd, James Allan Kahle, Hung Q. Le, Kevin F. Reick | 2003-04-01 |
| 6529979 | Method and apparatus for a high-speed serial communications bus protocol with positive acknowledgement | Michael Stephen Floyd, Kevin F. Reick | 2003-03-04 |
| 6393594 | Method and system for performing pseudo-random testing of an integrated circuit | Carl J. Anderson, Michael Stephen Floyd, Bradley McCredie, Kevin F. Reick, Jennifer L. Vargus | 2002-05-21 |