Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11875095 | Method for latency detection on a hardware simulation accelerator | Tharunachalam Pindicura, Shricharan Srivatsan, Vivek Britto, Madhumitha Venkataraman | 2024-01-16 |
| 11556365 | Obscuring information in virtualization environment | Debapriya Chatterjee, Bryant Cockcroft, Karen Yokum | 2023-01-17 |
| 11475191 | Generating and adding additional control information to logic under test to facilitate debugging and comprehension of a simulation | Paul Umbarger, Debapriya Chatterjee, Karen Yokum, Bryant Cockcroft, Kevin Barnett | 2022-10-18 |
| 11436013 | Method and system for detection of thread stall | Omesh Bajaj, Kevin Barnett, Debapriya Chatterjee, Bryant Cockcroft, Jamory Hawkins +7 more | 2022-09-06 |
| 11347505 | Processor performance monitor that logs reasons for reservation loss | Shakti Kapoor, Karen Yokum | 2022-05-31 |
| 11301392 | Address translation cache invalidation in a microprocessor | Debapriya Chatterjee, Bryant Cockcroft, Larry Scott Leitner, Karen Yokum | 2022-04-12 |
| 11243864 | Identifying translation errors | Bryant Cockcroft, Debapriya Chatterjee, Larry Scott Leitner, Kevin Barnett, Karen Yokum | 2022-02-08 |
| 11157285 | Dynamic modification of instructions that do not modify the architectural state of a processor | Bryant Cockcroft, Karen Yokum, Vivek Britto, Debapriya Chatterjee | 2021-10-26 |
| 11138089 | Performance benchmark generation | Shricharan Srivatsan, Vivek Britto, Aishwarya Dhandapani, Tharunachalam Pindicura, Brian W. Thompto | 2021-10-05 |
| 11080122 | Software-invisible interrupt for a microprocessor | Larry Scott Leitner, Debapriya Chatterjee, Wallace Sharp, Bryant Cockcroft | 2021-08-03 |
| 10942853 | System and method including broadcasting an address translation invalidation instruction with a return marker to indentify the location of data in a computing system having mutiple processors | Debapriya Chatterjee, Bryant Cockcroft, Lawrence Leitner, Karen Yokum | 2021-03-09 |
| 10915456 | Address translation cache invalidation in a microprocessor | Debapriya Chatterjee, Bryant Cockcroft, Larry Scott Leitner, Karen Yokum | 2021-02-09 |
| 10896273 | Precise verification of a logic problem on a simulation accelerator | Debapriya Chatterjee, Bryant Cockcroft, Kevin Barnett, Piriya K. Hall, Paul Umbarger +1 more | 2021-01-19 |
| 10754791 | Software translation prefetch instructions | Vivek Britto, Bryant Cockcroft, Tharunachalam Pindicura, Shricharan Srivatsan, Yan Xia +1 more | 2020-08-25 |
| 10705843 | Method and system for detection of thread stall | Omesh Bajaj, Kevin Barnett, Debapriya Chatterjee, Bryant Cockcroft, Jamory Hawkins +7 more | 2020-07-07 |
| 10579376 | Processor performance monitor that logs reasons for reservation loss | Shakti Kapoor, Karen Yokum | 2020-03-03 |
| 10539614 | Circuit design verification in a hardware accelerated simulation environment using breakpoints | Rahul Batra, Debapriya Chatterjee, John C. Goss, Christopher R. Jones, Christopher M. Riedl +1 more | 2020-01-21 |
| 10228422 | Driving pervasive commands using breakpoints in a hardware-accelerated simulation environment | Debapriya Chatterjee, Shakti Kapoor | 2019-03-12 |
| 10007568 | Testing a non-core MMU | Manoj Dusanapudi, Shakti Kapoor, Paul Frank Lecocq | 2018-06-26 |
| 9939487 | Circuit design verification in a hardware accelerated simulation environment using breakpoints | Rahul Batra, Debapriya Chatterjee, John C. Goss, Christopher R. Jones, Christopher M. Riedl +1 more | 2018-04-10 |
| 9921897 | Testing a non-core MMU | Manoj Dusanapudi, Shakti Kapoor, Paul Frank Lecocq | 2018-03-20 |
| 9747396 | Driving pervasive commands using breakpoints in a hardware-accelerated simulation environment | Debapriya Chatterjee, Shakti Kapoor | 2017-08-29 |
| 8832502 | Hardware verification using acceleration platform | Manoj Dusanapudi, Wisam Kadry, Shakti Kapoor, Dimtry Krestyashyn, Shimon Landa +3 more | 2014-09-09 |
| 8073668 | Method and apparatus for testing a full system integrated circuit design by statistical fault injection using hardware-based simulation | Jeffrey William Kellington, Prabhakar Kudva, Naoko Pia Sanda | 2011-12-06 |