Issued Patents All Time
Showing 1–25 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12141071 | Performance and reliability of processor store operation data transfers | Nelson Wu, Manoj Dusanapudi | 2024-11-12 |
| 12130749 | Validation of store coherence relative to page translation invalidation | Nelson Wu, Manoj Dusanapudi | 2024-10-29 |
| 12118355 | Cache coherence validation using delayed fulfillment of L2 requests | Manoj Dusanapudi, Nelson Wu | 2024-10-15 |
| 11620235 | Validation of store coherence relative to page translation invalidation | Nelson Wu, Manoj Dusanapudi | 2023-04-04 |
| 11501046 | Pre-silicon chip model of extracted workload inner loop instruction traces | Nelson Wu, Daniel I. Rodriguez, Miguel Gomez Gonzalez | 2022-11-15 |
| 11347505 | Processor performance monitor that logs reasons for reservation loss | Karen Yokum, John A. Schumann | 2022-05-31 |
| 11163704 | Method, system, and apparatus for reducing processor latency | — | 2021-11-02 |
| 11151011 | Uncore input/output latency analysis | Daniel I. Rodriguez, Miguel Gomez Gonzalez, Anatoli Andreev | 2021-10-19 |
| 11094391 | List insertion in test segments with non-naturally aligned data boundaries | Manoj Dusanapudi, Nelson Wu | 2021-08-17 |
| 11061821 | Method, system, and apparatus for stress testing memory translation tables | Manoj Dusanapudi, Nelson Wu | 2021-07-13 |
| 10983798 | Transactional memory performance and footprint | — | 2021-04-20 |
| 10977043 | Transactional memory performance and footprint | — | 2021-04-13 |
| 10877864 | Controlling segment layout in a stress test for a processor memory with a link stack | Manoj Dusanapudi | 2020-12-29 |
| 10748637 | System and method for testing processor errors | Nelson Wu, Manoj Dusanapudi, Nandhini Rajaiah | 2020-08-18 |
| 10713179 | Efficiently generating effective address translations for memory management test cases | Manoj Dusanapudi | 2020-07-14 |
| 10579376 | Processor performance monitor that logs reasons for reservation loss | John A. Schumann, Karen Yokum | 2020-03-03 |
| 10540249 | Stress testing a processor memory with a link stack | Manoj Dusanapudi | 2020-01-21 |
| 10528476 | Embedded page size hint for page fault resolution | — | 2020-01-07 |
| 10521355 | Method, system, and apparatus for stress testing memory translation tables | Manoj Dusanapudi, Nelson Wu | 2019-12-31 |
| 10489259 | Replicating test case data into a cache with non-naturally aligned data boundaries | Manoj Dusanapudi | 2019-11-26 |
| 10489261 | Efficient testing of direct memory address translation | Manoj Dusanapudi, Nelson Wu | 2019-11-26 |
| 10481991 | Efficient testing of direct memory address translation | Manoj Dusanapudi, Nelson Wu | 2019-11-19 |
| 10482040 | Method, system, and apparatus for reducing processor latency | — | 2019-11-19 |
| 10438682 | List insertion in test segments with non-naturally aligned data boundaries | Manoj Dusanapudi, Nelson Wu | 2019-10-08 |
| 10417129 | Transactional memory operation success rate | — | 2019-09-17 |