Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12141071 | Performance and reliability of processor store operation data transfers | Shakti Kapoor, Manoj Dusanapudi | 2024-11-12 |
| 12130749 | Validation of store coherence relative to page translation invalidation | Shakti Kapoor, Manoj Dusanapudi | 2024-10-29 |
| 12118355 | Cache coherence validation using delayed fulfillment of L2 requests | Shakti Kapoor, Manoj Dusanapudi | 2024-10-15 |
| 11620235 | Validation of store coherence relative to page translation invalidation | Shakti Kapoor, Manoj Dusanapudi | 2023-04-04 |
| 11501046 | Pre-silicon chip model of extracted workload inner loop instruction traces | Daniel I. Rodriguez, Miguel Gomez Gonzalez, Shakti Kapoor | 2022-11-15 |
| 11094391 | List insertion in test segments with non-naturally aligned data boundaries | Manoj Dusanapudi, Shakti Kapoor | 2021-08-17 |
| 11061821 | Method, system, and apparatus for stress testing memory translation tables | Manoj Dusanapudi, Shakti Kapoor | 2021-07-13 |
| 10748637 | System and method for testing processor errors | Manoj Dusanapudi, Shakti Kapoor, Nandhini Rajaiah | 2020-08-18 |
| 10521355 | Method, system, and apparatus for stress testing memory translation tables | Manoj Dusanapudi, Shakti Kapoor | 2019-12-31 |
| 10489261 | Efficient testing of direct memory address translation | Manoj Dusanapudi, Shakti Kapoor | 2019-11-26 |
| 10481991 | Efficient testing of direct memory address translation | Manoj Dusanapudi, Shakti Kapoor | 2019-11-19 |
| 10438682 | List insertion in test segments with non-naturally aligned data boundaries | Manoj Dusanapudi, Shakti Kapoor | 2019-10-08 |
| 10169185 | Efficient testing of direct memory address translation | Manoj Dusanapudi, Shakti Kapoor | 2019-01-01 |
| 10169186 | Efficient testing of direct memory address translation | Manoj Dusanapudi, Shakti Kapoor | 2019-01-01 |