Issued Patents All Time
Showing 26–50 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10417129 | Transactional memory operation success rate | — | 2019-09-17 |
| 10346314 | Efficiently generating effective address translations for memory management test cases | Manoj Dusanapudi | 2019-07-09 |
| 10318456 | Validation of correctness of interrupt triggers and delivery | Manoj Dusanapudi, Brenton Yiu, Siva Sundar A | 2019-06-11 |
| 10261878 | Stress testing a processor memory with a link stack | Manoj Dusanapudi | 2019-04-16 |
| 10261917 | Identifying stale entries in address translation cache | Vinod Bussa, Manoj Dusanapudi | 2019-04-16 |
| 10241880 | Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems | Manoj Dusanapudi | 2019-03-26 |
| 10228422 | Driving pervasive commands using breakpoints in a hardware-accelerated simulation environment | Debapriya Chatterjee, John A. Schumann | 2019-03-12 |
| 10223225 | Testing speculative instruction execution with test cases placed in memory segments with non-naturally aligned data boundaries | Manoj Dusanapudi | 2019-03-05 |
| 10185692 | Monitoring use of specialized hardware components (SHC) of processors in heterogeneous environments by storing event counts during execution | Grace Y. Liu, Karen Yokum | 2019-01-22 |
| 10169180 | Replicating test code and test data into a cache with non-naturally aligned data boundaries | Manoj Dusanapudi | 2019-01-01 |
| 10169181 | Efficient validation of transactional memory in a computer processor | Vinod Bussa, Manoj Dusanapudi | 2019-01-01 |
| 10169185 | Efficient testing of direct memory address translation | Manoj Dusanapudi, Nelson Wu | 2019-01-01 |
| 10169186 | Efficient testing of direct memory address translation | Manoj Dusanapudi, Nelson Wu | 2019-01-01 |
| 10162754 | Lateral cast out of cache memory | — | 2018-12-25 |
| 10162763 | Invalidation of translation look-aside buffer entries by a guest operating system | — | 2018-12-25 |
| 10055320 | Replicating test case data into a cache and cache inhibited memory | Manoj Dusanapudi | 2018-08-21 |
| 10007568 | Testing a non-core MMU | Manoj Dusanapudi, Paul Frank Lecocq, John A. Schumann | 2018-06-26 |
| 9959182 | Replicating test case data into a cache with non-naturally aligned data boundaries | Manoj Dusanapudi | 2018-05-01 |
| 9959183 | Replicating test case data into a cache with non-naturally aligned data boundaries | Manoj Dusanapudi | 2018-05-01 |
| 9940226 | Synchronization of hardware agents in a computer system | Manoj Dusanapudi | 2018-04-10 |
| 9934118 | Reducing SPQL tester time for the critical paths stress test | — | 2018-04-03 |
| 9921897 | Testing a non-core MMU | Manoj Dusanapudi, Paul Frank Lecocq, John A. Schumann | 2018-03-20 |
| 9910780 | Pre-loading page table cache lines of a virtual machine | — | 2018-03-06 |
| 9904569 | Pre-loading page table cache lines of a virtual machine | — | 2018-02-27 |
| 9892060 | Identifying stale entries in address translation cache | Vinod Bussa, Manoj Dusanapudi | 2018-02-13 |