Issued Patents All Time
Showing 76–83 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7661023 | System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation | Sampan Arora, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Chakrapani Rayadurgam | 2010-02-09 |
| 7647539 | System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation | Vinod Bussa, Manoj Dusanapudi, Sunil Suresh Hatti, Rahul Sharad Moharil, Bhavani Shringari Nanjundiah | 2010-01-12 |
| 7584394 | System and method for pseudo-random test pattern memory allocation for processor design verification and validation | Shubhodeep Roy Choudhury, Sandip Bag, Manoj Dusanapudi, Sunil Suresh Hatti, Bhavani Shringari Nanjundiah | 2009-09-01 |
| 7529864 | Method and system for testing remote I/O functionality | Deepak C. Shetty | 2009-05-05 |
| 7249308 | Algorithm to test LPAR I/O subsystem's adherence to LPAR I/O firewalls | Daljeet Maini | 2007-07-24 |
| 6898734 | I/O stress test | Prashanth Kumar Adamane | 2005-05-24 |
| 6792514 | Method, system and computer program product to stress and test logical partition isolation features | Jayakumar N. Sankarannair | 2004-09-14 |
| 6357020 | Method and system for low level testing of central electronics complex hardware using Test nano Kernel | Theodore J. Bohizic, Walid Kobrosly | 2002-03-12 |