Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8099559 | System and method for generating fast instruction and data interrupts for processor design verification and validation | Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Rahul Sharad Moharil | 2012-01-17 |
| 8019566 | System and method for efficiently testing cache congruence classes during processor design verification and validation | Vinod Bussa, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Batchu Naga Venkata Satyanarayana | 2011-09-13 |
| 8006221 | System and method for testing multiple processor modes for processor design verification and validation | Sampan Arora, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Sai Rupak Mohanan | 2011-08-23 |
| 7992059 | System and method for testing a large memory area during processor design verification and validation | Divya S. Anvekar, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor | 2011-08-02 |
| 7752499 | System and method for using resource pools and instruction pools for processor design verification and validation | Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Rahul Sharad Moharil | 2010-07-06 |
| 7747908 | System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation | Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Chakrapani Rayadurgam, Batchu Naga Venkata Satyanarayana | 2010-06-29 |
| 7739570 | System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation | Sandip Bag, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Rahul Sharad Moharil | 2010-06-15 |
| 7669083 | System and method for re-shuffling test case instruction orders for processor design verification and validation | Sampan Arora, Sandip Bag, Vinod Bussa, Manoj Dusanapudi, Sunil Suresh Hatti +3 more | 2010-02-23 |
| 7661023 | System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation | Sampan Arora, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Chakrapani Rayadurgam | 2010-02-09 |
| 7584394 | System and method for pseudo-random test pattern memory allocation for processor design verification and validation | Sandip Bag, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Bhavani Shringari Nanjundiah | 2009-09-01 |