Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8019566 | System and method for efficiently testing cache congruence classes during processor design verification and validation | Vinod Bussa, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor | 2011-09-13 |
| 7797650 | System and method for testing SLB and TLB cells during processor design verification and validation | Sandip Bag, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor | 2010-09-14 |
| 7747908 | System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation | Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Chakrapani Rayadurgam | 2010-06-29 |
| 7669083 | System and method for re-shuffling test case instruction orders for processor design verification and validation | Sampan Arora, Sandip Bag, Vinod Bussa, Shubhodeep Roy Choudhury, Manoj Dusanapudi +3 more | 2010-02-23 |