Issued Patents All Time
Showing 51–75 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9798667 | Streaming stress testing of cache memory | — | 2017-10-24 |
| 9747396 | Driving pervasive commands using breakpoints in a hardware-accelerated simulation environment | Debapriya Chatterjee, John A. Schumann | 2017-08-29 |
| 9720845 | Identifying stale entries in address translation cache | Vinod Bussa, Manoj Dusanapudi | 2017-08-01 |
| 9697138 | Identifying stale entries in address translation cache | Vinod Bussa, Manoj Dusanapudi | 2017-07-04 |
| 9612929 | Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems | Manoj Dusanapudi | 2017-04-04 |
| 9594680 | Identifying stale entries in address translation cache | Vinod Bussa, Manoj Dusanapudi | 2017-03-14 |
| 9542290 | Replicating test case data into a cache with non-naturally aligned data boundaries | Manoj Dusanapudi | 2017-01-10 |
| 9501408 | Efficient validation of coherency between processor cores and accelerators in computer systems | Manoj Dusanapudi, Sairam Kamaraju | 2016-11-22 |
| 8832502 | Hardware verification using acceleration platform | Manoj Dusanapudi, Wisam Kadry, Dimtry Krestyashyn, Shimon Landa, Amir Nahir +3 more | 2014-09-09 |
| 8185694 | Testing real page number bits in a cache directory | Shiraz M. Zaman | 2012-05-22 |
| 8145819 | Method and system for stealing interrupt vectors | Sangram Alapati, Brad L. Herold, Alexandru Adrian Patrascu | 2012-03-27 |
| 8127192 | Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode | Sampan Arora, Divya S. Anvekar, Manoj Dusanapudi, Sunil Suresh Hatti, Bhavani Shringari Nanjundiah | 2012-02-28 |
| 8099559 | System and method for generating fast instruction and data interrupts for processor design verification and validation | Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Rahul Sharad Moharil | 2012-01-17 |
| 8037215 | Performance evaluation of algorithmic tasks and dynamic parameterization on multi-core processing systems | John A. Gunnels, Ravi Kothari, Yogish Sabharwal, James C. Sexton | 2011-10-11 |
| 8019566 | System and method for efficiently testing cache congruence classes during processor design verification and validation | Vinod Bussa, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Batchu Naga Venkata Satyanarayana | 2011-09-13 |
| 8006221 | System and method for testing multiple processor modes for processor design verification and validation | Sampan Arora, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Sai Rupak Mohanan | 2011-08-23 |
| 7992059 | System and method for testing a large memory area during processor design verification and validation | Divya S. Anvekar, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti | 2011-08-02 |
| 7966521 | Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics | Vinod Bussa, Manoj Dusanapudi, Sunil Suresh Hatti | 2011-06-21 |
| 7797650 | System and method for testing SLB and TLB cells during processor design verification and validation | Sandip Bag, Manoj Dusanapudi, Sunil Suresh Hatti, Batchu Naga Venkata Satyanarayana | 2010-09-14 |
| 7793011 | Performance evaluation of algorithmic tasks and dynamic parameterization on multi-core processing systems | John A. Gunnels, Ravi Kothari, Yogish Sabharwal, James C. Sexton | 2010-09-07 |
| 7752499 | System and method for using resource pools and instruction pools for processor design verification and validation | Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Rahul Sharad Moharil | 2010-07-06 |
| 7747908 | System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation | Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Chakrapani Rayadurgam, Batchu Naga Venkata Satyanarayana | 2010-06-29 |
| 7739570 | System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation | Sandip Bag, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Rahul Sharad Moharil | 2010-06-15 |
| 7689886 | System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation | Sampan Arora, Divya S. Anvekar, Manoj Dusanapudi, Sunil Suresh Hatti, Bhavani Shringari Nanjundiah | 2010-03-30 |
| 7669083 | System and method for re-shuffling test case instruction orders for processor design verification and validation | Sampan Arora, Sandip Bag, Vinod Bussa, Shubhodeep Roy Choudhury, Manoj Dusanapudi +3 more | 2010-02-23 |