Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Address translation cache invalidation in a microprocessor

Address translation cache invalidation in a microprocessor

US Patent 10915456 · Granted Feb 9, 2021

Estimated economic value: $3,536,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Hardware-based implementation of secure hash algorithms2025
Hardware-based message block padding for hash algorithms2025
Systems and methods for dynamic control of a secure mode of operation in a proce2025
Comparing hash values computed at function entry and exit for increased security2024
Secure memory isolation for secure endpoints2024
Method and system for on demand control of hardware support for software pointer2024
Method for latency detection on a hardware simulation accelerator2024
Methods and systems to discover special outcomes in an instruction set architect2023
Methods and systems to discover special outcomes in an instruction set architect2023
Systems and methods for dynamic control of a secure mode of operation in a proce2023
Detecting deviations from targeted design performance in accelerator/emulator en2023
Obscuring information in virtualization environment2023