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Memory sharing across distributed nodes |
Paul N. Loewenstein, John G. Johnson, Zoran Radovic |
2019-03-05 |
| 10180913 |
Secure virtual access for real-time embedded devices |
Leslie D. Kohn, Robert C. Kunz, Jenn-Yuan Tsai |
2019-01-15 |
| 10055224 |
Reconfigurable hardware structures for functional pipelining of on-chip special purpose functions |
Garret F. Swart |
2018-08-21 |
| 10007629 |
Inter-processor bus link and switch chip failure recovery |
Thomas M. Wicki, David Richard Smentek, Sumti Jairath, Ali Vahidsafa, Paul N. Loewenstein |
2018-06-26 |
| 9836326 |
Cache probe request to optimize I/O directed caching |
David Richard Smentek, Sumti Jairath, Manling Yang, Serena Leung, Paul N. Loewenstein |
2017-12-05 |
| 9600412 |
Secure virtual access for real-time embedded devices |
Leslie D. Kohn, Robert C. Kunz, Jenn-Yuan Tsai |
2017-03-21 |
| 9571408 |
Dynamic flow control using credit sharing |
Manling Yang, David Richard Smentek |
2017-02-14 |
| 9542443 |
Hardware for performing a database operation |
Garret F. Swart, Sanjiv Kapil |
2017-01-10 |
| 9292569 |
Semi-join acceleration |
Garret F. Swart |
2016-03-22 |
| 9251272 |
Reconfigurable hardware structures for functional pipelining of on-chip special purpose functions |
Garret F. Swart |
2016-02-02 |
| 9158810 |
Hardware message queues for intra-cluster communication |
William Bridge, Garret F. Swart, Sumti Jairath, John G. Johnson |
2015-10-13 |
| 9146879 |
Virtual memory management for real-time embedded devices |
Leslie D. Kohn, Robert C. Kunz, Jenn-Yuan Tsai |
2015-09-29 |
| 9063974 |
Hardware for table scan acceleration |
Garret F. Swart, Sanjiv Kapil |
2015-06-23 |
| 8868883 |
Virtual memory management for real-time embedded devices |
Leslie D. Kohn, Robert C. Kunz, Jenn-Yuan Tsai |
2014-10-21 |
| 8756605 |
Method and apparatus for scheduling multiple threads for execution in a shared microprocessor pipeline |
Hong Su |
2014-06-17 |
| 8694755 |
Virtual memory management for real-time embedded devices |
Leslie D. Kohn, Robert C. Kunz, Jenn-Yuan Tsai |
2014-04-08 |
| 7421382 |
Data analysis techniques for dynamic power simulation of a CPU |
Miriam G. Blatt, David Greenhill, Claude Gauthier |
2008-09-02 |
| 7310709 |
Method and apparatus for primary cache tag error handling |
Ramaswamy Sivaramakrishnan, Sanjay Patel |
2007-12-18 |
| 7203100 |
Efficient implementation of a read scheme for multi-threaded register file |
Shree Kant, Yuan Lin, Kenway Tam |
2007-04-10 |
| 7136308 |
Efficient method of data transfer between register files and memories |
Shree Kant, Kenway Tam, Poonacha Kongetira, Yuan Lin, Zhen Liu |
2006-11-14 |
| 6587815 |
Windowing scheme for analyzing noise from multiple sources |
Manjunath D. Haritsa, Lakshminarasimhan Varadadesikan |
2003-07-01 |
| 6536022 |
Two pole coupling noise analysis model for submicron integrated circuit design verification |
Edgardo F. Klass, Chaim Amir, Chin Kim |
2003-03-18 |
| 6507935 |
Method of analyzing crosstalk in a digital logic integrated circuit |
Chin Kim, Hong You |
2003-01-14 |
| 6449753 |
Hierarchical coupling noise analysis for submicron integrated circuit designs |
Joydeep Mitra |
2002-09-10 |
| 6335639 |
Non-monotonic dynamic exclusive-OR/NOR gate circuit |
— |
2002-01-01 |
