Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9817762 | Facilitating efficient prefetching for scatter/gather operations | Darryl J. Gove | 2017-11-14 |
| 9542443 | Hardware for performing a database operation | Kathirgamar Aingaran, Garret F. Swart | 2017-01-10 |
| 9400821 | Memory bus protocol to enable clustering between nodes of distinct physical domain address spaces | Zoran Radovic | 2016-07-26 |
| 9372813 | Remote-key based memory buffer access control mechanism | Garret F. Swart, Aings Aingaran, William Bridge, Sumti Jairath, John G. Johnson | 2016-06-21 |
| 9208084 | Extended main memory hierarchy having flash memory for page fault handling | Ricky C. Hetherington | 2015-12-08 |
| 9180034 | Device for assisting weight control | — | 2015-11-10 |
| 9063974 | Hardware for table scan acceleration | Kathirgamar Aingaran, Garret F. Swart | 2015-06-23 |
| 8819359 | Hybrid interleaving in memory modules by interleaving physical addresses for a page across ranks in a memory module | Blake A. Jones | 2014-08-26 |
| 8208467 | Method and apparatus for modulating the width of a high-speed link | David Greenhill, Robert P. Masleid | 2012-06-26 |
| 8180981 | Cache coherent support for flash in a memory hierarchy | Ricky C. Hetherington | 2012-05-15 |
| 8166316 | Single interface access to multiple bandwidth and power memory zones | — | 2012-04-24 |
| 8127153 | Memory power profiling | — | 2012-02-28 |
| 7523282 | Clock enable throttling for power savings in a memory subsystem | Aaron S. Wynn | 2009-04-21 |
| 7496777 | Power throttling in a memory system | — | 2009-02-24 |
| 7263586 | Cache coherency for multiple independent cache of a domain | — | 2007-08-28 |
| 6735707 | Hardware architecture for a multi-mode power management system using a constant time reference for operating system support | — | 2004-05-11 |
| 6668330 | Constant time reference for OS support in different frequency modes | — | 2003-12-23 |