DG

David Greenhill

Oracle: 18 patents #515 of 14,854Top 4%
SD Satcom Direct: 1 patents #16 of 26Top 65%
IN Intel: 1 patents #18,218 of 30,777Top 60%
Overall (All Time): #206,587 of 4,157,543Top 5%
21
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11475719 Automated flight operations system James W. Jensen, Jason Natwick, Greg Romano, Brian Rudloff, Derek Donahue +1 more 2022-10-18
11334263 Configuration or data caching for programmable logic device Scott J. Weber, Sean R. Atsatt, Ravi Prakash Gutala, Aravind Raghavendra Dasu, Jun Tan 2022-05-17
10049508 Automated flight operations system James W. Jensen, Jason Natwick, Greg Romano, Brian Rudloff, Derek Donahue +1 more 2018-08-14
8648645 Microprocessor performance and power optimization through self calibrated inductive voltage droop monitoring and correction Georgios Konstadinidis, Sudhakar Bobba 2014-02-11
8283960 Minimal bubble voltage regulator Hanh-Phuc Le, Robert P. Masleid 2012-10-09
8269544 Power-supply noise suppression using a frequency-locked loop Robert P. Masleid, Georgios Konstadinidis, King Yen, Sebastian Turullols 2012-09-18
8208467 Method and apparatus for modulating the width of a high-speed link Sanjiv Kapil, Robert P. Masleid 2012-06-26
8198931 Fine grain timing Hanh-Phuc Le, Robert P. Masleid 2012-06-12
7872516 Precision pulse generator Robert P. Masleid 2011-01-18
7816966 Economy precision pulse generator Robert P. Masleid, Bijoy Kalloor 2010-10-19
7532003 Method and apparatus for setting VDD on a per chip basis Curtis R. McAllister, Thomas Caron, Shanker Bhagvat 2009-05-12
7421382 Data analysis techniques for dynamic power simulation of a CPU Miriam G. Blatt, Claude Gauthier, Kathirgamar Aingaran 2008-09-02
7418582 Versatile register file design for a multi-threaded processor utilizing different modes and register windows Sorin Iacobovici, Daniel Leibholz 2008-08-26
7098501 Thin capacitive structure Weiran Kong, Bernard W. K. Ho, Sudhakar Bobba 2006-08-29
7000164 Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip flops Joseph Siegel, Ban Wong 2006-02-14
6993103 Method for synchronizing clock and data signals Tyler Thorp, James Tran, Gin Yee 2006-01-31
6895561 Power modeling methodology for a pipelined processor Miriam G. Blatt, Poonacha Kongetira, Vidyasagar Ganesan 2005-05-17
6570407 Scannable latch for a dynamic circuit Junji Sugisawa, Larry Kan, Joseph Siegel 2003-05-27
6426652 Dual-edge triggered dynamic logic Pradeep Trivedi 2002-07-30
H1796 Method and circuit for eliminating hold time violations in synchronous Chakra R. Srivatsa, Ronald J. Melanson 1999-07-06
5668490 Flip-flop with full scan capability Sundari Mitra, Philip Ferolito 1997-09-16