Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8648645 | Microprocessor performance and power optimization through self calibrated inductive voltage droop monitoring and correction | Georgios Konstadinidis, David Greenhill | 2014-02-11 |
| 8060766 | Microprocessor performance and power optimization through inductive voltage droop monitoring and correction | Georgios Konstadinidis | 2011-11-15 |
| 7155695 | Signal shielding technique using active shields for non-interacting driver design | Tyler Thorp | 2006-12-26 |
| 7098501 | Thin capacitive structure | Weiran Kong, Bernard W. K. Ho, David Greenhill | 2006-08-29 |
| 6976235 | Region-based voltage drop budgets for low-power design | Gin Yee, Pradeep Trivedi | 2005-12-13 |
| 6971079 | Accuracy of timing analysis using region-based voltage drop budgets | Gin Yee, Pradeep Trivedi | 2005-11-29 |
| 6882196 | Duty cycle corrector | Gin Yee, Claude Gauthier, Dean Liu, Lynn Ooi, Pradeep Trivedi | 2005-04-19 |
| 6861885 | Phase locked loop design with diode for loop filter capacitance leakage current control | Pradeep Trivedi, Claude Gauthier | 2005-03-01 |
| 6784689 | Transmission gate based signal transition accelerator | Pradeep Trivedi | 2004-08-31 |
| 6762505 | 150 degree bump placement layout for an integrated circuit power grid | Tyler Thorp, Dean Liu, Pradeep Trivedi | 2004-07-13 |
| 6737844 | Dynamic modulation of on-chip supply voltage for low-power design | Pradeep Trivedi | 2004-05-18 |
| 6721936 | Shield assignment using preferential shields | Tyler Thorp | 2004-04-13 |
| 6708314 | Clock skew reduction using active shields | Pradeep Trivedi | 2004-03-16 |
| 6694493 | Decoupling capacitance assignment technique with minimum leakage power | Tyler Thorp | 2004-02-17 |
| 6687886 | Logic optimization for preferential shields | Tyler Thorp | 2004-02-03 |
| 6658629 | Technique for optimizing decoupling capacitance subject to leakage power constraints | Pradeep Trivedi, Tyler Thorp | 2003-12-02 |
| 6653857 | Increasing implicit decoupling capacitance using asymmetric shieldings | Tyler Thorp | 2003-11-25 |
| 6646472 | Clock power reduction technique using multi-level voltage input clock driver | Pradeep Trivedi | 2003-11-11 |
| 6646473 | Multiple supply voltage dynamic logic | Pradeep Trivedi | 2003-11-11 |
| 6642756 | Frequency multiplier design | Gin Yee, Lynn Ooi, Pradeep Trivedi | 2003-11-04 |
| 6640331 | Decoupling capacitor assignment technique with respect to leakage power | Pradeep Trivedi, Tyler Thorp | 2003-10-28 |
| 6628138 | Increasing decoupling capacitance using preferential shields | Tyler Thorp | 2003-09-30 |
| 6629306 | Signal routing based approach for increasing decoupling capacitance using preferential shielding | Tyler Thorp | 2003-09-30 |
| 6625791 | Sliding grid based technique for optimal on-chip decap insertion | Pradeep Trivedi | 2003-09-23 |
| 6617699 | 120 degree bump placement layout for an integrated circuit power grid | Tyler Thorp, Dean Liu | 2003-09-09 |