Issued Patents All Time
Showing 25 most recent of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12231821 | Display method, display device and computer-readable storage medium | — | 2025-02-18 |
| 8638896 | Repeate architecture with single clock multiplier unit | Marc Loinaz, Stefanos Sidiropoulos | 2014-01-28 |
| 8433018 | Methods and apparatus for frequency synthesis with feedback interpolation | Stefanos Sidiropoulos, Marc Loinaz, R. Sekhar Narayanaswami, Nikhil Acharya | 2013-04-30 |
| 7978802 | Method and apparatus for a mesochronous transmission system | Prasun K. Raha, Donald C. Stark, Pak Shing Chau | 2011-07-12 |
| 7913104 | Method and apparatus for receive channel data alignment with minimized latency variation | Warren E. Cory, Donald C. Stark, Clemenz Portmann | 2011-03-22 |
| 7724815 | Method and apparatus for a programmably terminated receiver | Prasun K. Raha | 2010-05-25 |
| 7489982 | Method and software for conducting efficient lithography WPH / lost time analysis in semiconductor manufacturing | Kun Liu | 2009-02-10 |
| 7436229 | Methods and apparatus for minimizing jitter in a clock synthesis circuit that uses feedback interpolation | Stefanos Sidiropoulos, Marc Loinaz, R. Shekhar Narayanaswami, Nikhil Acharya | 2008-10-14 |
| 7432750 | Methods and apparatus for frequency synthesis with feedback interpolation | Stefanos Sidiropoulos, Marc Loinaz, R. Shekhar Narayanaswami, Nikhil Acharya | 2008-10-07 |
| 7323916 | Methods and apparatus for generating multiple clocks using feedback interpolation | Stefanos Sidiropoulos, Marc Loinaz, R. Shekhar Narayanaswami, Nikhil Acharya | 2008-01-29 |
| 7251305 | Method and apparatus to store delay locked loop biasing parameters | Claude Gauthier, Brian Amick, Pradeep Trivedi | 2007-07-31 |
| 7136799 | Mixed signal delay locked loop characterization engine | Kian Haur Chong, Claude Gauthier | 2006-11-14 |
| 7106113 | Adjustment and calibration system for post-fabrication treatment of phase locked loop input receiver | Claude Gauthier, Brian Amick, Pradeep Trivedi | 2006-09-12 |
| 7062688 | Updating high speed parallel I/O interfaces based on counters | Claude Gauthier, Aninda Roy, Brian Amick | 2006-06-13 |
| 6882196 | Duty cycle corrector | Gin Yee, Sudhakar Bobba, Claude Gauthier, Lynn Ooi, Pradeep Trivedi | 2005-04-19 |
| 6819192 | Jitter estimation for a phase locked loop | Claude Gauthier, Brian Amick, Pradeep Trivedi | 2004-11-16 |
| 6815986 | Design-for-test technique for a delay locked loop | Aninda Roy, Claude Gauthier, Brian Amick | 2004-11-09 |
| 6809557 | Increasing power supply noise rejection using linear voltage regulators in an on-chip temperature sensor | Claude Gauthier, Spencer Gold, Kamran Zarrineh, Brian Amick, Pradeep Trivedi | 2004-10-26 |
| 6806698 | Quantifying a difference between nodal voltages | Claude Gauthier, Brian Amick, Spencer Gold, Kamran Zarrineh, Pradeep Trivedi | 2004-10-19 |
| 6788045 | Method and apparatus for calibrating a delay locked loop charge pump current | Claude Gauthier, Brian Amick, Pradeep Trivedi | 2004-09-07 |
| 6784752 | Post-silicon phase offset control of phase locked loop input receiver | Claude Gauthier, Brian Amick, Pradeep Trivedi | 2004-08-31 |
| 6768955 | Adjustment and calibration system for post-fabrication treatment of phase locked loop charge pump | Claude Gauthier, Brian Amick, Pradeep Trivedi | 2004-07-27 |
| 6762505 | 150 degree bump placement layout for an integrated circuit power grid | Sudhakar Bobba, Tyler Thorp, Pradeep Trivedi | 2004-07-13 |
| 6753740 | Method and apparatus for calibration of a post-fabrication bias voltage tuning feature for self biasing phase locked loop | Claude Gauthier, Brian Amick, Pradeep Trivedi | 2004-06-22 |
| 6748339 | Method for simulating power supply noise in an on-chip temperature sensor | Brian Amick, Claude Gauthier, Pradeep Trivedi | 2004-06-08 |