Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7436229 | Methods and apparatus for minimizing jitter in a clock synthesis circuit that uses feedback interpolation | Stefanos Sidiropoulos, Marc Loinaz, Nikhil Acharya, Dean Liu | 2008-10-14 |
| 7432750 | Methods and apparatus for frequency synthesis with feedback interpolation | Stefanos Sidiropoulos, Marc Loinaz, Nikhil Acharya, Dean Liu | 2008-10-07 |
| 7323916 | Methods and apparatus for generating multiple clocks using feedback interpolation | Stefanos Sidiropoulos, Marc Loinaz, Nikhil Acharya, Dean Liu | 2008-01-29 |