Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8090930 | Method and circuits for early detection of a full queue | Timothy C. Fischer, James Arthur Farrell | 2012-01-03 |
| 7493615 | Apparatus and method for synchronizing multiple threads in an out-of-order microprocessor | Evan Gewirtz, Todd David Basso, Benjamin C. Cordes | 2009-02-17 |
| 7418582 | Versatile register file design for a multi-threaded processor utilizing different modes and register windows | Sorin Iacobovici, David Greenhill | 2008-08-26 |
| 6954846 | MICROPROCESSOR AND METHOD FOR GIVING EACH THREAD EXCLUSIVE ACCESS TO ONE REGISTER FILE IN A MULTI-THREADING MODE AND FOR GIVING AN ACTIVE THREAD ACCESS TO MULTIPLE REGISTER FILES IN A SINGLE THREAD MODE | Wayne Yamamoto | 2005-10-11 |
| 6813702 | Methods and apparatus for generating effective test code for out of order super scalar microprocessors | Carl Ramey | 2004-11-02 |
| 6704856 | Method for compacting an instruction queue | James Arthur Farrell, Timothy C. Fischer, Bruce Gieseke | 2004-03-09 |
| 6675288 | Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list | James Arthur Farrell, Sharon Marie Britton, Harry Ray Fair, III, Bruce Gieseke, Derrick R. Meyer | 2004-01-06 |
| 6662293 | Instruction dependency scoreboard with a hierarchical structure | Richard H. Larson, Sanjay Patel, Poonacha Kongetira | 2003-12-09 |
| 6542987 | Method and circuits for early detection of a full queue | Timothy C. Fischer, James Arthur Farrell | 2003-04-01 |
| 6449713 | Implementation of a conditional move instruction in an out-of-order processor | Joel S. Emer, Bruce E. Edwards, Edward J. McLellan, Derrick R. Meyer | 2002-09-10 |
| 6405304 | Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list | James Arthur Farrell, Sharon Marie Britton, Harry Ray Fair, III, Bruce Gieseke, Derrick R. Meyer | 2002-06-11 |
| 6195748 | Apparatus for sampling instruction execution information in a processor pipeline | George Z. Chrysos, Jeffrey Adgate Dean, James E. Hicks, Carl A. Waldspurger, William E. Weihl +1 more | 2001-02-27 |
| 6163840 | Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline | George Z. Chrysos, Jeffrey Adgate Dean, James E. Hicks, Edward J. McLellan, Carl A. Waldspurger +1 more | 2000-12-19 |
| 6141734 | Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol | Rahul Razdan, David A. Webb, James B. Keller, Derrick R. Meyer | 2000-10-31 |
| 6122728 | Technique for ordering internal processor register accesses | Sharon Marie Britton, James Arthur Farrell, Timothy C. Fischer | 2000-09-19 |
| 6098166 | Speculative issue of instructions under a load miss shadow | Sven Meier, James Arthur Farrell, Timothy C. Fischer, Derrick R. Meyer | 2000-08-01 |
| 6000044 | Apparatus for randomly sampling instructions in a processor pipeline | George Z. Chrysos, Jeffrey Adgate Dean, James E. Hicks, Edward J. McLellan, Carl A. Waldspurger +1 more | 1999-12-07 |
| 5103393 | Method of dynamically allocating processors in a massively parallel processing system | Jonathan Harris, Brad Miller | 1992-04-07 |