Issued Patents All Time
Showing 25 most recent of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10776022 | Combined transparent/non-transparent cache | James Wang, Zongjian Chen, Timothy J. Millet | 2020-09-15 |
| 10241705 | Combined transparent/non-transparent cache | James Wang, Zongjian Chen, Timothy J. Millet | 2019-03-26 |
| 9575754 | Zero cycle move | John H. Mylius, Conrado Blasco-Allue, Gerard R. Williams, III, Suparn Vats | 2017-02-21 |
| 9529544 | Combined transparent/non-transparent cache | James Wang, Zongjian Chen, Timothy J. Millet | 2016-12-27 |
| 9430243 | Optimizing register initialization operations | John H. Mylius, Conrado Blasco-Allue, Gerard R. Williams, III | 2016-08-30 |
| 9317285 | Instruction set architecture mode dependent sub-size access of register with associated status indication | Sandeep Gupta, Conrado Blasco-Allue, John H. Mylius, Gerard R. Williams, III | 2016-04-19 |
| 9274953 | Combined transparent/non-transparent cache | James Wang, Zongjian Chen, Timothy J. Millet | 2016-03-01 |
| 9223577 | Processing multi-destination instruction in pipeline by splitting for single destination operations stage and merging for opcode execution operations stage | John H. Mylius, Gerard R. Williams, III, Fang Liu, Shyam Sundar | 2015-12-29 |
| 9201658 | Branch predictor for wide issue, arbitrarily aligned fetch that can cross cache line boundaries | Ian D. Kountanis, Gerard R. Williams, III | 2015-12-01 |
| 8977818 | Combined transparent/non-transparent cache | James Wang, Zongjian Chen, Timothy J. Millet | 2015-03-10 |
| 8848577 | Bandwidth management | Gurjeet S. Saund, Manu Gulati, Sukalpa Biswas | 2014-09-30 |
| 8775757 | Trust zone support in system on a chip having security enclave processor | R. Stephen Polzin, Gerard R. Williams, III | 2014-07-08 |
| 8744602 | Fabric limiter circuits | Gurjeet S. Saund, Michael Frank | 2014-06-03 |
| 8719509 | Cache implementing multiple replacement policies | James Wang, Zongjian Chen, Timothy J. Millet | 2014-05-06 |
| 8611127 | Stacked memory device having a scalable bandwidth interface | Patrick Law, R. Stephen Polzin | 2013-12-17 |
| 8566526 | Combined transparent/non-transparent cache | James Wang, Zongjian Chen, Timothy J. Millet | 2013-10-22 |
| 8493863 | Hierarchical fabric control circuits | Gurjeet S. Saund, Michael Frank | 2013-07-23 |
| 8392658 | Cache implementing multiple replacement policies | James Wang, Zongjian Chen, Timothy J. Millet | 2013-03-05 |
| 8359414 | Retry mechanism | Sridhar Subramanian, Ramesh Gunna | 2013-01-22 |
| 8301941 | Memory controller with loopback test interface | Luka Bodrozic, Sukalpa Biswas, Hao Chen, Sridhar Subramanian | 2012-10-30 |
| 8255670 | Replay reduction for power saving | Po-Yung Chang, Wei-Han Lien, Jesse Pan, Ramesh Gunna, Tse-Yu Yeh | 2012-08-28 |
| 8244981 | Combined transparent/non-transparent cache | James Wang, Zongjian Chen, Timothy J. Millet | 2012-08-14 |
| 8219758 | Block-based non-transparent cache | James Wang, Zongjian Chen, Timothy J. Millet | 2012-07-10 |
| 8218347 | Stacked memory device having a scalable bandwidth interface | Patrick Law, R. Stephen Polzin | 2012-07-10 |
| 8171326 | L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down | Tse-Yu Yeh, Ramesh Gunna, Brian J. Campbell | 2012-05-01 |