Issued Patents All Time
Showing 51–75 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6952791 | Method and circuit for initializing a de-skewing buffer in a clock forwarded system | Daniel W. Dobberpuhl | 2005-10-04 |
| 6950438 | System and method for implementing a separate virtual channel for posted requests in a multiprocessor computer system | Jonathan Owen, Mark Hummel | 2005-09-27 |
| 6941406 | System having interfaces and switch that separates coherent and packet traffic | Barton Sano, Joseph B. Rowlands, Laurent Moll, Koray Oner, Manu Gulati | 2005-09-06 |
| 6938094 | Virtual channels and corresponding buffer allocations for deadlock-free computer system operation | Derrick R. Meyer | 2005-08-30 |
| 6928500 | High speed bus system that incorporates uni-directional point-to-point buses | Raj K. Ramanujan, William A. Samaras, John DeRosa, Robert Eugene Stewart | 2005-08-09 |
| 6888843 | Response virtual channel for handling all responses | Derrick R. Meyer | 2005-05-03 |
| 6877076 | Memory controller with programmable configuration | James Y. Cho, Mark D. Hayter | 2005-04-05 |
| 6851004 | Adaptive retry mechanism | Chun Ning, Kwong-Tak Chui, Mark D. Hayter | 2005-02-01 |
| 6848024 | Programmably disabling one or more cache entries | Joseph B. Rowlands | 2005-01-25 |
| 6748442 | Method and apparatus for using a control signal on a packet based communication link | — | 2004-06-08 |
| 6748479 | System having interfaces and switch that separates coherent and packet traffic | Barton Sano, Joseph B. Rowlands, Laurent Moll, Koray Oner, Manu Gulati | 2004-06-08 |
| 6745272 | System and method of increasing bandwidth for issuing ordered transactions into a distributed communication system | Jonathan Owen, Mark Hummel, Derrick R. Meyer | 2004-06-01 |
| 6738896 | Method and apparatus for determining availability of a queue which allows random insertion | David A. Webb, Derrick R. Meyer | 2004-05-18 |
| 6728841 | Conserving system memory bandwidth during a memory read operation in a multiprocessing computer system | — | 2004-04-27 |
| 6721813 | Computer system implementing a system and method for tracking the progress of posted write transactions | Jonathan Owen, Mark Hummel | 2004-04-13 |
| 6714994 | Host bridge translating non-coherent packets from non-coherent link to coherent packets on conherent link and vice versa | Derrick R. Meyer | 2004-03-30 |
| 6704854 | Determination of execution resource allocation based on concurrently executable misaligned memory operations | Stephan G. Meier | 2004-03-09 |
| 6694424 | Store load forward predictor training | Thomas S. Green, Wei-Han Lien, Ramsey W. Haddad | 2004-02-17 |
| 6687789 | Cache which provides partial tags from non-predicted ways to direct search if way prediction misses | Keith R. Schakel, Puneet Sharma | 2004-02-03 |
| 6651161 | Store load forward predictor untraining | Thomas S. Green, Wei-Han Lien, Ramsey W. Haddad | 2003-11-18 |
| 6651144 | Method and apparatus for developing multiprocessor cache control protocols using an external acknowledgement signal to set a cache to a dirty state | Rahul Razdan, Richard E. Kessler | 2003-11-18 |
| 6647490 | Training line predictor for branch targets | Puneet Sharma, Keith R. Schakel, Francis Matus | 2003-11-11 |
| 6636959 | Predictor miss decoder updating line predictor storing instruction fetch address and alignment information upon instruction decode termination condition | Puneet Sharma, Keith R. Schakel, Francis Matus | 2003-10-21 |
| 6633936 | Adaptive retry mechanism | Chun Ning, Kwong-Tak Chui, Mark D. Hayter | 2003-10-14 |
| 6631401 | Flexible probe/probe response routing for maintaining coherency | Dale E. Gulick | 2003-10-07 |