| 12360769 |
Branch target buffer operation with auxiliary indirect cache |
Chandramouli Banerjee, Rabin Sugumar |
2025-07-15 |
|
| 7991922 |
System on a chip for networking |
Mark D. Hayter, Joseph B. Rowlands |
2011-08-02 |
$5,041,000 |
| 7660931 |
System on a chip for networking |
Mark D. Hayter, Joseph B. Rowlands |
2010-02-09 |
$6,739,000 |
| 7418534 |
System on a chip for networking |
Mark D. Hayter, Joseph B. Rowlands |
2008-08-26 |
$10,809,000 |
| 7093052 |
Bus sampling on one edge of a clock signal and driving on another edge |
Joseph B. Rowlands |
2006-08-15 |
$8,857,000 |
| 7076582 |
Bus precharge during a phase of a clock signal to eliminate idle clock cycle |
Joseph B. Rowlands, Mark Pearce |
2006-07-11 |
$15,697,000 |
| 6877076 |
Memory controller with programmable configuration |
James B. Keller, Mark D. Hayter |
2005-04-05 |
$8,888,000 |
| 6865633 |
Independent reset of arbiters and agents to allow for delayed agent reset |
Joseph B. Rowlands, David L. Anderson |
2005-03-08 |
$7,227,000 |
| 6816932 |
Bus precharge during a phase of a clock signal to eliminate idle clock cycle |
Joseph B. Rowlands, Mark Pearce |
2004-11-09 |
$9,541,000 |
| 6766389 |
System on a chip for networking |
Mark D. Hayter, Joseph B. Rowlands |
2004-07-20 |
$15,876,000 |
| 6681302 |
Page open hint in transactions |
Kwong-Tak Chui, Chun Ning |
2004-01-20 |
$39,034,000 |
| 6678767 |
Bus sampling on one edge of a clock signal and driving on another edge |
Joseph B. Rowlands |
2004-01-13 |
$31,765,000 |
| 6633938 |
Independent reset of arbiters and agents to allow for delayed agent reset |
Joseph B. Rowlands, David L. Anderson |
2003-10-14 |
$39,210,000 |
| 6629218 |
Out of order associative queue in two clock domains |
— |
2003-09-30 |
$23,829,000 |
| 6625685 |
Memory controller with programmable configuration |
James B. Keller, Mark D. Hayter |
2003-09-23 |
$25,210,000 |
| 6526483 |
Page open hint in transactions |
Kwong-Tak Chui, Chun Ning |
2003-02-25 |
$7,773,000 |
| 6449701 |
Out of order associative queue in two clock domains |
— |
2002-09-10 |
$28,488,000 |
| 6321300 |
Apparatus and method for dynamically reconfigurable timed flushing of a queue of coalescing write buffers |
Matthew D. Ornes |
2001-11-20 |
|
| 6240532 |
Programmable hit and write policy for cache memory test |
— |
2001-05-29 |
|
| 5255384 |
Memory address translation system having modifiable and non-modifiable translation mechanisms |
Howard G. Sachs |
1993-10-19 |
$4,802,000 |
| 5091846 |
Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency |
Howard G. Sachs |
1992-02-25 |
$10,751,000 |
| 4933835 |
Apparatus for maintaining consistency of a cache memory with a primary memory |
Howard G. Sachs, Walter H. Hollingsworth |
1990-06-12 |
$8,670,000 |
| 4899275 |
Cache-MMU system |
Howard G. Sachs, Walter H. Hollingsworth |
1990-02-06 |
$7,730,000 |
| 4884197 |
Method and apparatus for addressing a cache memory |
Howard G. Sachs, Walter H. Hollingsworth |
1989-11-28 |
$7,679,000 |
| 4860192 |
Quadword boundary cache system |
Howard G. Sachs, Walter H. Hollingsworth |
1989-08-22 |
$9,351,000 |
