Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12360769 | Branch target buffer operation with auxiliary indirect cache | Chandramouli Banerjee, Rabin Sugumar | 2025-07-15 |
| 7991922 | System on a chip for networking | Mark D. Hayter, Joseph B. Rowlands | 2011-08-02 |
| 7660931 | System on a chip for networking | Mark D. Hayter, Joseph B. Rowlands | 2010-02-09 |
| 7418534 | System on a chip for networking | Mark D. Hayter, Joseph B. Rowlands | 2008-08-26 |
| 7093052 | Bus sampling on one edge of a clock signal and driving on another edge | Joseph B. Rowlands | 2006-08-15 |
| 7076582 | Bus precharge during a phase of a clock signal to eliminate idle clock cycle | Joseph B. Rowlands, Mark Pearce | 2006-07-11 |
| 6877076 | Memory controller with programmable configuration | James B. Keller, Mark D. Hayter | 2005-04-05 |
| 6865633 | Independent reset of arbiters and agents to allow for delayed agent reset | Joseph B. Rowlands, David L. Anderson | 2005-03-08 |
| 6816932 | Bus precharge during a phase of a clock signal to eliminate idle clock cycle | Joseph B. Rowlands, Mark Pearce | 2004-11-09 |
| 6766389 | System on a chip for networking | Mark D. Hayter, Joseph B. Rowlands | 2004-07-20 |
| 6681302 | Page open hint in transactions | Kwong-Tak Chui, Chun Ning | 2004-01-20 |
| 6678767 | Bus sampling on one edge of a clock signal and driving on another edge | Joseph B. Rowlands | 2004-01-13 |
| 6633938 | Independent reset of arbiters and agents to allow for delayed agent reset | Joseph B. Rowlands, David L. Anderson | 2003-10-14 |
| 6629218 | Out of order associative queue in two clock domains | — | 2003-09-30 |
| 6625685 | Memory controller with programmable configuration | James B. Keller, Mark D. Hayter | 2003-09-23 |
| 6526483 | Page open hint in transactions | Kwong-Tak Chui, Chun Ning | 2003-02-25 |
| 6449701 | Out of order associative queue in two clock domains | — | 2002-09-10 |
| 6321300 | Apparatus and method for dynamically reconfigurable timed flushing of a queue of coalescing write buffers | Matthew D. Ornes | 2001-11-20 |
| 6240532 | Programmable hit and write policy for cache memory test | — | 2001-05-29 |
| 5255384 | Memory address translation system having modifiable and non-modifiable translation mechanisms | Howard G. Sachs | 1993-10-19 |
| 5091846 | Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency | Howard G. Sachs | 1992-02-25 |
| 4933835 | Apparatus for maintaining consistency of a cache memory with a primary memory | Howard G. Sachs, Walter H. Hollingsworth | 1990-06-12 |
| 4899275 | Cache-MMU system | Howard G. Sachs, Walter H. Hollingsworth | 1990-02-06 |
| 4884197 | Method and apparatus for addressing a cache memory | Howard G. Sachs, Walter H. Hollingsworth | 1989-11-28 |
| 4860192 | Quadword boundary cache system | Howard G. Sachs, Walter H. Hollingsworth | 1989-08-22 |