Mark Pearce — 13 Patents at Broadcom

Mark Pearce has been granted 13 US patents while listed as an inventor at Broadcom. The first was granted in 2003 and the most recent in February 2024. Mark Pearce ranks #362,438 of 4,157,543 US inventors in our database (top 8.7%). Patent records list Mark Pearce in San Francisco, CA, US.

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
11914440	Protocol level control for system on a chip (SoC) agent reset and power management	Shailendra Desai, Amit Jain, Jaymin Patel	2024-02-27	$97,983,000
11640362	Procedures for improving efficiency of an interconnect fabric on a system on chip	Shailendra Desai, Robert Totte, Juan Sierra, Parimal Gaikwad, Amit Jain	2023-05-02	$214,592,000
11340671	Protocol level control for system on a chip (SOC) agent reset and power management	Shailendra Desai, Amit Jain, Jaymin Patel	2022-05-24	$54,647,000
11003604	Procedures for improving efficiency of an interconnect fabric on a system on chip	Shailendra Desai, Robert Totte, Juan Sierra, Parimal Gaikwad, Amit Jain	2021-05-11
10853282	Arbitrating portions of transactions over virtual channels associated with an interconnect	Shailendra Desai, Amit Jain, Rutul Bhatt	2020-12-01
10838891	Arbitrating portions of transactions over virtual channels associated with an interconnect	Shailendra Desai, Amit Jain, Rutul Bhatt	2020-11-17
10585825	Procedures for implementing source based routing within an interconnect fabric on a system on chip	Shailendra Desai, Robert Totte, Juan Sierra, Parimal Gaikwad, Amit Jain	2020-03-10
7162613	Mechanism for processing speculative LL and SC instructions in a pipelined processor	Tse-Yu Yeh, Po-Yung Chang, Zongjian Chen	2007-01-09	$11,189,000
7076582	Bus precharge during a phase of a clock signal to eliminate idle clock cycle	James Y. Cho, Joseph B. Rowlands	2006-07-11	$15,697,000
6877085	Mechanism for processing speclative LL and SC instructions in a pipelined processor	Tse-Yu Yeh, Po-Yung Chang, Zongjian Chen	2005-04-05	$8,888,000
6816932	Bus precharge during a phase of a clock signal to eliminate idle clock cycle	James Y. Cho, Joseph B. Rowlands	2004-11-09	$9,541,000
6785152	Content addressable memory with power reduction technique	George Kong Yiu	2004-08-31	$11,122,000
6646899	Content addressable memory with power reduction technique	George Kong Yiu	2003-11-11	$30,544,000

Mark Pearce — 13 Patents

Issued Patents All Time

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