PG

Parimal Gaikwad

AR Arteris: 9 patents #3 of 48Top 7%
Google: 1 patents #14,769 of 22,993Top 65%
📍 San Jose, CA: #5,375 of 32,062 inventorsTop 20%
🗺 California: #50,852 of 386,348 inventorsTop 15%
Overall (All Time): #406,933 of 4,157,543Top 10%
12
Patents All Time

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDate
11640362 Procedures for improving efficiency of an interconnect fabric on a system on chip Shailendra Desai, Robert Totte, Juan Sierra, Amit Jain, Mark Pearce 2023-05-02
11513892 System and method for using a directory to recover a coherent system from an uncorrectable error 2022-11-29
11416352 System and method for logic functional redundancy Jean Philippe Loison, Benoit de LESCURE, Alexis Boutiller, Rohit Bansal, Mohammed Khaleeluddin 2022-08-16
11385957 System for memory access bandwidth management using ECC 2022-07-12
11003604 Procedures for improving efficiency of an interconnect fabric on a system on chip Shailendra Desai, Robert Totte, Juan Sierra, Amit Jain, Mark Pearce 2021-05-11
10877839 Recovery of a coherent system in the presence of an uncorrectable error 2020-12-29
10866854 System and method for reducing ECC overhead and memory access bandwidth 2020-12-15
10592358 Functional interconnect redundancy in cache coherent systems Benoit deLESCURE, Jean Philippe Loison, Alexis Boutiller, Rohit Bansal 2020-03-17
10585825 Procedures for implementing source based routing within an interconnect fabric on a system on chip Shailendra Desai, Robert Totte, Juan Sierra, Amit Jain, Mark Pearce 2020-03-10
10452266 Directory storage control for commonly used patterns 2019-10-22
10452272 System to reduce directory information storage 2019-10-22
10146615 Recovery of a system directory after detection of uncorrectable error 2018-12-04