Issued Patents All Time
Showing 25 most recent of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8566528 | Combining write buffer with dynamically adjustable flush metrics | Peter J. Bannon, Andrew J. Beaumont-Smith, Ramesh Gunna, Wei-Han Lien, Brian P. Lilly +2 more | 2013-10-22 |
| 8352685 | Combining write buffer with dynamically adjustable flush metrics | Peter J. Bannon, Andrew J. Beaumont-Smith, Ramesh Gunna, Wei-Han Lien, Brian P. Lilly +2 more | 2013-01-08 |
| 8255670 | Replay reduction for power saving | Po-Yung Chang, Wei-Han Lien, Jesse Pan, Ramesh Gunna, James B. Keller | 2012-08-28 |
| 8171240 | Misalignment predictor | Po-Yung Chang, Eric Hao | 2012-05-01 |
| 8171326 | L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down | James B. Keller, Ramesh Gunna, Brian J. Campbell | 2012-05-01 |
| 8117404 | Misalignment predictor | Po-Yung Chang, Eric Hao | 2012-02-14 |
| 7996646 | Efficient encoding for detecting load dependency on store with misalignment | Daniel C. Murray, Po-Yung Chang, Anup S. Mehta | 2011-08-09 |
| 7752474 | L1 cache flush when processor is entering low power mode | James B. Keller, Ramesh Gunna, Brian J. Campbell | 2010-07-06 |
| 7721066 | Efficient encoding for detecting load dependency on store with misalignment | Daniel C. Murray, Po-Yung Chang, Anup S. Mehta | 2010-05-18 |
| 7647518 | Replay reduction for power saving | Po-Yung Chang, Wei-Han Lien, Jesse Pan, Ramesh Gunna, James B. Keller | 2010-01-12 |
| 7269714 | Inhibiting of a co-issuing instruction in a processor having different pipeline lengths | David A. Kruckemyer, Robert Rogenmoser | 2007-09-11 |
| 7203817 | Power consumption reduction in a pipeline by stalling instruction issue on a load miss | — | 2007-04-10 |
| 7162613 | Mechanism for processing speculative LL and SC instructions in a pipelined processor | Po-Yung Chang, Mark Pearce, Zongjian Chen | 2007-01-09 |
| 7100064 | Limiting performance in an integrated circuit to meet export restrictions | Robert Rogenmoser, Michael Kim | 2006-08-29 |
| 6976152 | Comparing operands of instructions against a replay scoreboard to detect an instruction replay and copying a replay scoreboard to an issue scoreboard | David A. Kruckemyer, Randel Blake-Campos, Robert Rogenmoser, Robert Stepanian | 2005-12-13 |
| 6877085 | Mechanism for processing speclative LL and SC instructions in a pipelined processor | Po-Yung Chang, Mark Pearce, Zongjian Chen | 2005-04-05 |
| 6871275 | Microprocessor having a branch predictor using speculative branch registers | Mitchell Alexander Poplingher | 2005-03-22 |
| 6629238 | Predicate controlled software pipelined loop processing with prediction of predicate writing and value prediction for use in subsequent iteration | Judge K. Arora | 2003-09-30 |
| 6611910 | Method for processing branch operations | Harshvardhan Sharangpani, Michael Corwin, Millind Mittal, Kent Fielden, Dale Morris +3 more | 2003-08-26 |
| 6553488 | Method and apparatus for branch prediction using first and second level branch prediction tables | Harshvardhan Sharangpani | 2003-04-22 |
| 6542981 | Microcode upgrade and special function support by executing RISC instruction to invoke resident microcode | Nazar Zaidi, Gary N. Hammond, Kin-Yip Liu | 2003-04-01 |
| 6438682 | Method and apparatus for predicting loop exit branches | Dale Morris, Mircea Poplingher, Michael Corwin, Wenliang Chen | 2002-08-20 |
| 6430674 | Processor executing plural instruction sets (ISA's) with ability to have plural ISA's in different pipeline stages at same time | Jignesh Jagdishbhai Trivedi | 2002-08-06 |
| 6427206 | Optimized branch predictions for strongly predicted compiler branches | Mitchell Alexander Poplingher, Monis Rahman | 2002-07-30 |
| 6353805 | Apparatus and method for cycle accounting in microprocessors | Achmed R. Zahir, Vincent E. Hummel, Ralph M. Kling | 2002-03-05 |