Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12026095 | Cache coherent system implementing victim buffers | Craig S. Forrest | 2024-07-02 |
| 11507510 | Method for using victim buffer in cache coherent systems | Craig S. Forrest | 2022-11-22 |
| 11237965 | Configurable snoop filters for cache coherent systems | Craig S. Forrest | 2022-02-01 |
| 11080191 | Configurable snoop filters for cache coherent systems | Craig S. Forrest | 2021-08-03 |
| 10255183 | Victim buffer for cache coherent systems | Craig S. Forrest | 2019-04-09 |
| 10133671 | Proxy cache conditional allocation | Craig S. Forrest | 2018-11-20 |
| 9807025 | System and method for ordering of data transferred over multiple channels | Randal G. Martin, Steven C. Miller, Mark D. Stadler | 2017-10-31 |
| 9652391 | Compression of hardware cache coherent addresses | Craig S. Forrest | 2017-05-16 |
| 9542316 | System and method for adaptation of coherence models between agents | Craig S. Forrest | 2017-01-10 |
| 9432299 | System and method for ordering of data transferred over multiple channels | Randal G. Martin, Steven C. Miller, Mark D. Stadler | 2016-08-30 |
| 9280479 | Multi-level store merging in a cache and memory hierarchy | John G. Favor, Matthew William Ashcraft | 2016-03-08 |
| 9213643 | Broadcast messaging and acknowledgment messaging for power management in a multiprocessor system | John G. Favor | 2015-12-15 |
| 8971329 | System and method for ordering of data transferred over multiple channels | Randal G. Martin, Steven C. Miller, Mark D. Stadler | 2015-03-03 |
| 8850121 | Outstanding load miss buffer with shared entries | Matthew William Ashcraft, John G. Favor | 2014-09-30 |
| 8806135 | Load store unit with load miss result buffer | Matthew William Ashcraft, John G. Favor | 2014-08-12 |
| 8793435 | Load miss result buffer with shared data lines | Matthew William Ashcraft, John G. Favor | 2014-07-29 |
| 7453878 | System and method for ordering of data transferred over multiple channels | Randal G. Martin, Steven C. Miller, Mark D. Stadler | 2008-11-18 |
| 7437597 | Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines | Kevin Normoyle, Jack Choquette | 2008-10-14 |
| 7366847 | Distributed cache coherence at scalable requestor filter pipes that accumulate invalidation acknowledgements from other requestor filter pipes using ordering messages from central snoop tag | Kevin Normoyle, Robert Hathaway | 2008-04-29 |
| 7296141 | Method for cancelling speculative conditional delay slot instructions | — | 2007-11-13 |
| 7269714 | Inhibiting of a co-issuing instruction in a processor having different pipeline lengths | Tse-Yu Yeh, Robert Rogenmoser | 2007-09-11 |
| 7225300 | Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system | Jack Choquette, Robert Hathaway | 2007-05-29 |
| 7219216 | Method for identifying basic blocks with conditional delay slot instructions | — | 2007-05-15 |
| 7203827 | Link and fall-through address formation using a program counter portion selected by a specific branch address bit | Daniel C. Murray | 2007-04-10 |
| 6993632 | Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent | Joseph B. Rowlands | 2006-01-31 |