Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12287745 | Direct memory access architecture with multi-level multi-striding | Mark William Gottscho, Thomas Norrie, Oliver Bowen | 2025-04-29 |
| 12164917 | Transposing at-speed in a vector-matrix accelerator | Vinayak Anand Gokhale, Matthew Leever Hedlund, Indranil Chakraborty | 2024-12-10 |
| 11762793 | Direct memory access architecture with multi-level multi-striding | Mark William Gottscho, Thomas Norrie, Oliver Bowen | 2023-09-19 |
| 11744748 | Dryness layer laminate for absorbent articles | Harry Chmielewski, Michael Kalmon, Paul M. Ducker | 2023-09-05 |
| 11513798 | Implementation of load acquire/store release instructions using load/store operation with DMB operation | Christopher Patrick Nelson | 2022-11-29 |
| 11314674 | Direct memory access architecture with multi-level multi-striding | Mark William Gottscho, Thomas Norrie, Oliver Bowen | 2022-04-26 |
| 11093401 | Hazard prediction for a group of memory access instructions using a buffer associated with branch prediction | Richard Win Thaik | 2021-08-17 |
| 10348281 | Clock control based on voltage associated with a microprocessor | David S. Oliver, Luca Ravezzi, Alfred Yeung, John G. Favor | 2019-07-09 |
| 9880849 | Allocation of load instruction(s) to a queue buffer in a processor system based on prediction of an instruction pipeline hazard | Richard Win Thaik | 2018-01-30 |
| 9280479 | Multi-level store merging in a cache and memory hierarchy | David A. Kruckemyer, John G. Favor | 2016-03-08 |
| 8949581 | Threshold controlled limited out of order load execution | John G. Favor | 2015-02-03 |
| 8850121 | Outstanding load miss buffer with shared entries | John G. Favor, David A. Kruckemyer | 2014-09-30 |
| 8806135 | Load store unit with load miss result buffer | John G. Favor, David A. Kruckemyer | 2014-08-12 |
| 8793435 | Load miss result buffer with shared data lines | John G. Favor, David A. Kruckemyer | 2014-07-29 |
| 8499293 | Symbolic renaming optimization of a trace | John G. Favor, Christopher Patrick Nelson, Ivan Pavle Radivojevic, Joseph B. Rowlands, Richard Win Thaik | 2013-07-30 |
| 8037285 | Trace unit | Richard Win Thaik, John G. Favor, Joseph B. Rowlands, Leonard Eric Shar, Ivan Pavle Radivojevic | 2011-10-11 |
| 8032710 | System and method for ensuring coherency in trace execution | John G. Favor, Joseph B. Rowlands, Leonard Eric Shar, Richard Win Thaik | 2011-10-04 |
| 7941607 | Method and system for promoting traces in an instruction processing circuit | Richard Win Thaik, John G. Favor, Joseph B. Rowlands, Leonard Eric Shar | 2011-05-10 |
| 7937564 | Emit vector optimization of a trace | John G. Favor, Christopher Patrick Nelson, Ivan Pavle Radivojevic, Joseph B. Rowlands, Richard Win Thaik | 2011-05-03 |
| 7856548 | Prediction of data values read from memory by a microprocessor using a dynamic confidence threshold | Chris Nelson, John G. Favor | 2010-12-21 |
| 7849292 | Flag optimization of a trace | John G. Favor, Christopher Patrick Nelson, Ivan Pavle Radivojevic, Joseph B. Rowlands, Richard Win Thaik | 2010-12-07 |
| 7814298 | Promoting and appending traces in an instruction processing circuit based upon a bias value | Richard Win Thaik, John G. Favor, Joseph B. Rowlands, Leonard Eric Shar | 2010-10-12 |
| 7788473 | Prediction of data values read from memory by a microprocessor using the storage destination of a load operation | Chris Nelson, John G. Favor, Seungyoon Peter Song | 2010-08-31 |
| 7783863 | Graceful degradation in a trace-based processor | Christopher Patrick Nelson, John G. Favor, Richard Win Thaik | 2010-08-24 |